Computes TSEG size dynamically.
Changes the size of legacy hole to match other Intel northbirdges.
Refactor this a little by needing one less variable.
BUG=none
BRANCH=none
TEST=none
Change-Id: I71eccc97aee616652c992d87753c54a60fd1c023
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 4c4f56a6ba
Original-Change-Id: I0e6898c06a2bc1016eeaa3f002ff6c39657018ae
Original-Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Original-Reviewed-on: https://review.coreboot.org/18511
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://chromium-review.googlesource.com/501154
Change a4b11e5c90 (soc/intel/skylake: Perform CPU MP Init
before FSP-S Init) dropped mtrr_check while re-organizing
code. Add the check back after MTRR setup is performed.
BUG=b:36656098
TEST=Verified that MTRR check is done after setup on poppy.
Change-Id: If2f00fa65c716036bd5da37b9ba150460350cfbc
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: e411f8eb72
Original-Change-Id: I440405c58c470ffa338be386d84870635530a031
Original-Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/19609
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Philippe Mathieu-Daud <philippe.mathieu.daude@gmail.com>
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/501153
Configure the SD controller to handle the SD card slot.
* Galileo supports a removable SD card slot.
* Set SD card initialization frequency to 100 MHz.
* Set default removable delays.
* Build SD/MMC components by default
TEST=Build and run on Galileo Gen2
Change-Id: Icb6ca60d4f7ca9e7f6b387c622f7417713a2f9c7
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 1ea7cce8ae
Original-Change-Id: Iaf4faa40fe01eca98abffa2681f61fd8e059f0c4
Original-Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Original-Reviewed-on: https://review.coreboot.org/19212
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://chromium-review.googlesource.com/501152
With change a4b11e5c90 (soc/intel/skylake: Perform CPU MP Init
before FSP-S Init) to perform CPU MP init before FSP-S init, MTRR
programming was moved to be performed after CPU init is done. However,
in order to allow callbacks after MP init, PARALLEL_MP_AP_WORK needs
to be enabled. Since this option was not selected, MTRR programming
always failed in ramstage for Skylake / Kaby Lake mainboards.
BUG=b:36656098
TEST=Verified 2500+ cycles of suspend resume on poppy.
Change-Id: I1ca205254163b692221ad9178ddb9317e2731387
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: a585358f9b
Original-Change-Id: I22a8f6ac90ba35075ff97dd57bab66c129f3e771
Original-Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/19608
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/501151
The SD/MMC test support consists of:
* Add Kconfig value to enable the SD/MMC test support.
* Add Kconfig value to enable the logging support.
* Add SD/MMC controller init code and read block 0 from each partition.
* Add logging code to snapshot the transactions with the SD/MMC device.
* Add eMMC driver for ramstage to call test code.
* Add romstage code to call test code.
* Add bootblock code to call test code.
TEST=Build and run on Galileo Gen2
Change-Id: Id81621f1b40d95b8f8b48b396e38ec3912d17d9f
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 16bc9bab2a
Original-Change-Id: I72785f0dcd466c05c1385cef166731219b583551
Original-Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Original-Reviewed-on: https://review.coreboot.org/19211
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://chromium-review.googlesource.com/501150
This code ought not to run if ME is disabled. It also prohibits
writing to some GMCH regs like GGC bit1.
Intel 4 Series Chipset Family datasheet refers to this as
"ME stolen Memory lock" without actually describing this
functionality.
BUG=none
BRANCH=none
TEST=none
Change-Id: I2515e965aafbac95e78eef9a42ce10c302c892d7
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: ddc8828697
Original-Change-Id: Iaa8646e535e13c44c010ccd434a5af954cf7dfbc
Original-Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Original-Reviewed-on: https://review.coreboot.org/18513
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://chromium-review.googlesource.com/501147
This reverts commit 952d9af2ed.
I need to do an Eve BIOS release and this cannot be present yet as it
has to be released at the same time as the new touchpad firmware.
BUG=b:35581264
BRANCH=none
TEST=none
Change-Id: I35da873b5f071e803688ff8ccf08274303b8f228
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://chromium-review.googlesource.com/498587
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Provide a failing get_wifi_sar_limits() to allow SAR Kconfig
options to be selected without relying on CHROMEOS which currently
has the only code to provide SAR data.
BUG=none
BRANCH=none
TEST=none
Change-Id: I7f4de5de4bc3919de2a7236bf0dc8c41841634bf
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 2abbbf1503
Original-Change-Id: I1288871769014f4c4168da00952a1c563015de33
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/19580
Original-Reviewed-by: Furquan Shaikh <furquan@google.com>
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-on: https://chromium-review.googlesource.com/498348
Use `uintptr_t` instead of `uint32_t`, fixing the error below on 64-bit
systems, where pointers are 64-bit wide.
```
cc -O0 -g -Wall -W -Wno-unused-parameter -Wno-unused-but-set-variable -Wno-sign-compare -Wno-unused-function -c -o intelmetool.o intelmetool.c
intelmetool.c: In function dump_me_memory:
intelmetool.c:85:45: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast]
dump = map_physical_exact((off_t)me_clone, (void *)me_clone, 0x2000000);
^
```
BUG=https://ticket.coreboot.org/issues/111
Change-Id: I89c28fe9a3c5da1b2d5cad802624228680519567
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 57d912bacc
Original-Change-Id: Id8d778e97090668ad9308a82b44c6b2b599fd6c3
Original-Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Original-Reviewed-on: https://review.coreboot.org/19567
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Original-Reviewed-by: Philippe Mathieu-Daud <philippe.mathieu.daude@gmail.com>
Original-Reviewed-by: Paul Wise (Debian) <pabs@debian.org>
Reviewed-on: https://chromium-review.googlesource.com/498325
The device ids changed names between patches. Fix them to
not break the build any more.
BUG=none
BRANCH=none
TEST=none
Change-Id: I5e4a2522e45c5aa60db90b53aa7fd7c9b61bd572
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: f27d98fadc
Original-Change-Id: I1d74d95ec6b516c4d8354a714b2b302557743fe0
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/19600
Original-Reviewed-by: Furquan Shaikh <furquan@google.com>
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://chromium-review.googlesource.com/498324
spi_crop_chunk is a property of the SPI controller since it depends
upon the maximum transfer size that is supported by the
controller. Also, it is possible to implement this within spi-generic
layer by obtaining following parameters from the controller:
1. max_xfer_size: Maximum transfer size supported by the controller
(Size of 0 indicates invalid size, and unlimited transfer size is
indicated by UINT32_MAX.)
2. deduct_cmd_len: Whether cmd_len needs to be deducted from the
max_xfer_size to determine max data size that can be
transferred. (This is used by the amd boards.)
BUG=none
BRANCH=none
TEST=none
Change-Id: Iae7e196ab1e3fc1a665a4d27e722b920e78e8fd8
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: de705fa1f4
Original-Change-Id: I81c199413f879c664682088e93bfa3f91c6a46e5
Original-Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/19386
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Tested-by: coreboot org <coreboot.org@gmail.com>
Reviewed-on: https://chromium-review.googlesource.com/498323
Now that we have a common block driver for fast spi flash controller,
provide spi_ctrlr structure that can be used by different platforms
for defining the bus-ctrlr mapping. Only cs 0 is considered valid.
BUG=none
BRANCH=none
TEST=none
Change-Id: Ib4bf50bc9e72465e59aa82d1ca76f7e731bc8f2b
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: f1db5fdb4d
Original-Change-Id: I7228ae885018d1e23e6e80dd8ce227b0d99d84a6
Original-Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/19575
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-on: https://chromium-review.googlesource.com/498322
tis_close() must be called after tis_open() otherwise the locked
locality isn't released and the sessions hangs.
Tested=PC Engines APU2
BUG=none
BRANCH=none
TEST=none
Change-Id: Idd14621de1685ac965e96ba8b05365b829690e10
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 35418f9814
Original-Change-Id: I1a06f6a29015708e4bc1de6e6678827c28b84e98
Original-Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org>
Original-Reviewed-on: https://review.coreboot.org/19535
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://chromium-review.googlesource.com/498321
The AP sends the Cr50 a request to enable the new firmware image. If
the new Cr50 image was found and enabled, the AP expects the Cr50 to
reset the device in 1 second.
While waiting for the Cr50 to reset, the AP logs a newly defined event
and optionally shuts down the system. By default the x86 systems power
off as shutting those systems down is not board specific.
BRANCH=gru,reef
BUG=b:35580805
TEST=built a reef image, observed that in case cr50 image is updated,
after the next reboot the AP stops booting before loading depthcharge,
reports upcoming reset and waits for it.
Once the system is booted after that, the new event can be found
in the log:
localhost ~ # mosys eventlog list
...
7 | 2017-03-23 18:42:12 | Chrome OS Developer Mode
8 | 2017-03-23 18:42:13 | Unknown | 0xac
9 | 2017-03-23 18:42:21 | System boot | 46
...
Change-Id: I12706aebb64d6fb6b53386d8e9379b5781a7a84e
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: b9126fe46c
Original-Change-Id: I45fd6058c03f32ff8edccd56ca2aa5359d9b21b1
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/18946
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://chromium-review.googlesource.com/498315
Provide a common function to issue reboot commands to the EC.
Expose that function for external use and use it internal to
the module.
BUG=b:35580805
Change-Id: Ia0668359af2bb9acd0ad5c9086b63dcd3228e926
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: e68d22fbbc
Original-Change-Id: I1458bd7119b0df626a043ff3806c15ffb5446c9a
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/19573
Original-Reviewed-by: Furquan Shaikh <furquan@google.com>
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/498313
Use register name instead of hex values.
No functional change.
BUG=none
BRANCH=none
TEST=none
Change-Id: If7cb7a02841f960f547eaba62f9455499f6ad593
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: c368620d60
Original-Change-Id: I08fc8435f29ab87a0534946b0e0c43231919785d
Original-Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Original-Reviewed-on: https://review.coreboot.org/19545
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/498310
Use register name instead of hex value.
No functional change.
BUG=none
BRANCH=none
TEST=none
Change-Id: I3ed947b8d353083053e801d555239f2805bfe717
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 5c31af8e1a
Original-Change-Id: Iacfe609f6454e6d58c9733f425377464238ce4a9
Original-Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Original-Reviewed-on: https://review.coreboot.org/19544
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/498309
This patch adds the eMMC as one of the thermal sensor under DPTF.
Also, updates few comments for better interpretation and mapping.
BUG=None
BRANCH=None
TEST=Built for poppy.
Change-Id: I22edad5afd0e24fd19ee7857b750f0168d13a818
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: c9026b2945
Original-Change-Id: I6d05bb7a2f857dc5bc98227c8327b2ff1bd5b913
Original-Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Original-Reviewed-on: https://review.coreboot.org/19524
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/498308
Update the DPTF parameters based on thermal test result.
1. Update DPTF CPU/TSR0/TSR1/TSR2 passive/critial trigger points.
CPU passive point:83, critial point:99
TSR0 passive point:60, critial point:70
TSR1 passive point:50, critial point:90
TSR2 passive point:77, critial point:90
2. Update PL1/PL2 Min Power Limit/Max Power Limit
Set PL1 min to 4W, max to 12W, and step size to 0.2W
3. Change thermal relationship table (TRT) setting.
Change CPU Throttle Effect on CPU sample rate to 5secs
Change CPU Effect on Temp Sensor 0 sample rate to 60secs
The TRT of TCHG is TSR1, but real sensor is TSR2. sample rate to 30secs
Change Charger Effect on Temp Sensor 2 sample rate to 30secs
Change CPU Effect on Temp Sensor 2 sample rate to 120secs
BUG=None
TEST=build and boot on electro dut
Change-Id: I4488a6d4abbf90f34e5f7174ab71a6e62c5cb996
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 8caf8a23f9
Original-Change-Id: I0ea0bab7fa6b0ad75d9ddacbd7cd882f91e4b0db
Original-Signed-off-by: Katherine Hsieh <Katherine.Hsieh@quantatw.com>
Original-Reviewed-on: https://review.coreboot.org/19538
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/498307
NR indicates the last non empty region, which in this case is
GbE (region3). Needed for flashrom ifd layout support.
BUG=none
BRANCH=none
TEST=none
Change-Id: I981ff184dd4e8a88aaa103117d8c3991c08cc878
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 915a4cadf4
Original-Change-Id: I3f4dcb0d41718dd176982679f8e045681fd3f486
Original-Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Original-Reviewed-on: https://review.coreboot.org/19565
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Nico Huber <nico.h@gmx.de>
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://chromium-review.googlesource.com/497405
The current implementation is incorrect and is
actually disabling the ports. Fixes that.
BUG=b:37486021, b:35775024
BRANCH=None
TEST=reboot and ensure that we can boot from
SATA SSD.
Change-Id: I908c1ab04b6d5fd823a89bf1a1eae3116920e468
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: d44d028050
Original-Change-Id: I8525f6f5ddfdf61c564febd86b1ba2e01c22d9e5
Original-Signed-off-by: Shelley Chen <shchen@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/19553
Original-Reviewed-by: Furquan Shaikh <furquan@google.com>
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://chromium-review.googlesource.com/497404
Turn on device 1c.0 in order to enable devices
under it.
BUG=b:37486021, b:35775024
BRANCH=None
TEST=Boot from NVMe
Change-Id: I87c1f0a96067ec92f3df623f5327be243d53171f
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: f49785e8e2
Original-Change-Id: Ide66823283c58d2bea0c9886f762f0581741affe
Original-Signed-off-by: Shelley Chen <shchen@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/19533
Original-Reviewed-by: Furquan Shaikh <furquan@google.com>
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://chromium-review.googlesource.com/497403
This fixes a memory leak in the activate_me() function.
BUG=none
BRANCH=none
TEST=none
Change-Id: I6aa3de3547e685b31ef8391b08fdd7f11f12f87a
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 769f46625b
Original-Change-Id: I011b2f96122d8f88aed121352afe3f0d41edef60
Original-Signed-off-by: Paul Wise <pabs3@bonedaddy.net>
Original-Reviewed-on: https://review.coreboot.org/19561
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://chromium-review.googlesource.com/497401
These are more human readable for folks not familiar with errno values.
BUG=none
BRANCH=none
TEST=none
Change-Id: Idf092b591bd511f360e8cfec868e139083df5287
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 3c02699dd7
Original-Change-Id: I21352a00b583163472ccd3302a83adf1f8396c61
Original-Signed-off-by: Paul Wise <pabs3@bonedaddy.net>
Original-Reviewed-on: https://review.coreboot.org/19560
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Reviewed-on: https://chromium-review.googlesource.com/497400
This is required to ensure that SCI is generated whenever a host event
is set for MODE_CHANGE. Thus, when wake from MODE_CHANGE event occurs,
eSPI SCI is generated which results in kernel handler reading host
event from the EC and thus causes the wake pin to be de-asserted.
BUG=b:37223093
TEST=Verified that wake from mode change event works fine in suspend
mode and there is no interrupt storm for GPE SCI after resume.
Change-Id: Ib82e9291b55c68a4508bd1ce3f5f5ad08fdb228e
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 730fc6c7d8
Original-Change-Id: I1dd158ea0e302d5be9bcaa531cd1851082ba59fd
Original-Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/19559
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Jenny Tc <jenny.tc@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/497399
soc/i2c.h does not need to be included in this compilation unit.
BUG=none
BRANCH=none
TEST=none
Change-Id: I57bb42eb4565e9bf2faf7bce34b1115524e913dd
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: c2b1390d47
Original-Change-Id: Ife11642d2e69af7235c93fc54bba38853b046169
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/19572
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Furquan Shaikh <furquan@google.com>
Original-Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Original-Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://chromium-review.googlesource.com/497398
According to Yang York the FSP is responsible for switching the CPU into
high frequency mode (HFM). For an unknown reason this is not done for the
BSP on my platform though the APs are switched properly.
This code switches the CPU into HFM which makes sure that all cores are in
high frequency mode before payload is started.
It should not harm the operation even if FSP was successful in switching
to HFM.
BUG=none
BRANCH=none
TEST=none
Change-Id: Ia2e05152d0bfa7280d039c66c18eb5e38763c082
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: cf6392f756
Original-Change-Id: I91baf538511747d1692a8b6b359df5c3a8d56848
Original-Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Original-Reviewed-on: https://review.coreboot.org/19537
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/497397
Remove struct skylake_i2c_config from chip.h since it is not used
anymore.
BUG=none
BRANCH=none
TEST=none
Change-Id: I00e7670f3380e5ab23c5860ebe3fbde501d5bf65
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: bfcc1e37b9
Original-Change-Id: Icde4b7af5b9c31020099c1a6372a6867827f61ae
Original-Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/19520
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/497396
Currently native video init works on port HDMI1 (wired to the
on-board DVI-D socket) , HDMI3 (the on-board HDMI port), and the VGA
port, both text mode and fb mode.
Every ports works on GNU/Linux.
Tested against an IVB cpu (i7-3770T).
BUG=none
BRANCH=none
TEST=none
Change-Id: I637c593db52f54f044eb644dea0054c406e17c0a
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 91fbb25ec7
Original-Change-Id: If00a7247df0c32b3d1f489fb92d86baaa8fdf8ba
Original-Signed-off-by: Bill XIE <persmule@gmail.com>
Original-Reviewed-on: https://review.coreboot.org/19522
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Nico Huber <nico.h@gmx.de>
Original-Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://chromium-review.googlesource.com/497395
The checkreset() function checks if raminit previously
succeeded (pmcon2 bit7 == 0). If this is not the case it will issue a
hot reset (writing 0x6 to 0xcf9). On the next attempt to boot the
system BOOT_PATH_RESET path will be taken. This boot path can only
successfully initialize memory if the system was reset from a state
where raminit succeeded, which is not the case here.
This can be fixed by issuing a cold reset instead of a hot reset.
BUG=none
BRANCH=none
TEST=none
Change-Id: I4b9d826e63c89a67190c8acfe9ce8e459f77623e
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 8565c03caf
Original-Change-Id: Idbcf034c3777a64cc3fb92dc603d10470a6c8cb6
Original-Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Original-Reviewed-on: https://review.coreboot.org/19506
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://chromium-review.googlesource.com/497394
device is run before drivers to generate .config and the first default
takes precedence so this override achieves nothing.
BUG=none
BRANCH=none
TEST=none
Change-Id: I275e68349ad606785b444ccbb2fcefd459749e93
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: a93387b0d5
Original-Change-Id: Ib8d333a53a0dadcc94e47ca5460b23d49cf7eb52
Original-Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Original-Reviewed-on: https://review.coreboot.org/19511
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://chromium-review.googlesource.com/496056
Add some known good values for some thinkpads displays.
Known good means that at this pwm frequency the display is evenly lit
on all duty cycles, the display makes minimal to no noise at lower
duty cycles and the display does not flicker. This values differs from
vendor (which uses an obviously wrong display clock (190MHz instead
of 320MHz) resulting in frequency more than 60% off the intended
value.
TESTED on Thinkpad X200 with edid ascii string in list and removed
from list to see if notice message is shown.
BUG=none
BRANCH=none
TEST=none
Change-Id: I6df100df0f80ce479ace6ee2c1d59114c17f1a7a
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 20cb85fa98
Original-Change-Id: Id7bc0d453fac31e806852206ba2c895720b2c843
Original-Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Original-Reviewed-on: https://review.coreboot.org/19500
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://chromium-review.googlesource.com/496055
This allows to use EDID data outside of NGI path without needing to
fetch it twice.
BUG=none
BRANCH=none
TEST=none
Change-Id: Iae2da8ce54bcdbe4836a900bb0ef43b333366153
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 53485d2eab
Original-Change-Id: I6a540b1d036a9f38b44fd004309601630861f6e7
Original-Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Original-Reviewed-on: https://review.coreboot.org/19503
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://chromium-review.googlesource.com/496053
