Signed-off-by: Joseph Smith <joe@settoplinux.org>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@1170 f3766cd6-281f-0410-b1cd-43a5c92072e9
drop most of the crappy vm86 code and replace it with a rewritten
version that has all assembler in a .S file and all C code in a .c
file. Also, remove requirement to move around between GDTs.
This version includes the suggestions from Peter to clean up CR0 manipulation
and to guard critical code paths by cli/sti. Tested and working on my hardware.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@1167 f3766cd6-281f-0410-b1cd-43a5c92072e9
This patch makes it possible for Option ROMs to access devices
other than the one YABEL is running for. This is needed for some
onboard Graphics Cards Option ROMs.
Signed-off-by: Pattrick Hueper <phueper@hueper.net>
Tested and Acked-by: Joseph Smith <joe@settoplinux.org>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@1155 f3766cd6-281f-0410-b1cd-43a5c92072e9
It requires a flag (CONFIG_SCAN_BUILD) to be set, and then
$ scan-build make
Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@1146 f3766cd6-281f-0410-b1cd-43a5c92072e9
it in the v2 tree as well. Requires the yabel-prereq.diff patch in order to
work in v2.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Joseph Smith <joe@settoplinux.org>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@1141 f3766cd6-281f-0410-b1cd-43a5c92072e9
remove Makefile in yabel directory, since it is not needed (leftover
from SLOF biosemu)
fix dump() function output to not include \r
Signed-off-by: Pattrick Hueper <phueper@hueper.net>
Acked-by: Myles Watson <mylesgw@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@1082 f3766cd6-281f-0410-b1cd-43a5c92072e9
Subject: [PATCH] use the rom_addr passed by coreboot, needed for ROM images from LAR
Signed-off-by: Pattrick Hueper <phueper@hueper.net>
Acked-by: Myles Watson <mylesgw@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@1081 f3766cd6-281f-0410-b1cd-43a5c92072e9
were bridges as separate links. There isn't a board in v3 that needs multiple
links yet.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Marc Jones <marcj303@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@1079 f3766cd6-281f-0410-b1cd-43a5c92072e9
device/pci_device.c:
Only update IDs if:
- The device is on the mainboard
- The device has a Vendor ID and Device ID
- The device has a set_subsystem function in ops_pci(dev)
util/dtc/flattree.c:
Make devices from the dts be on_mainboard.
If they're plugged in, they shouldn't be in the dts.
mainboard/amd/serengeti/dts:
Add subsystem_vendor and subsystem_device.
Build tested on Serengeti. Getting closer :)
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@1045 f3766cd6-281f-0410-b1cd-43a5c92072e9
the console banner and the option table will never be updated with more
recent build.h strings.
Thanks to Mart Raudsepp for spotting this oddness.
x86emu doesn't care about the contents of build.h, it just uses build.h
to check whether it is compiled in conjunction with coreboot.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@1036 f3766cd6-281f-0410-b1cd-43a5c92072e9
This fixes one of the errors from using bison-2.4, but there are more.
This one in details is the following error:
BISON build/util/dtc/dtc-parser.tab.c
HOSTCC build/util/dtc/dtc-parser.tab.o
/home/leio/dev/coreboot-v3/util/dtc/dtc-parser.y: In function ‘yyuserAction’:
/home/leio/dev/coreboot-v3/util/dtc/dtc-parser.y:154: error: expected ‘;’ before ‘}’ token
make: *** [/home/leio/dev/coreboot-v3/build/util/dtc/dtc-parser.tab.o] Error 1
Note that 2.4.1 might be made to still work without the semi-colon for some languages, but I
understand 2.5 then still won't work without one. As it builds fine with this change with
bison-2.3, it should be safe to just add the semicolon.
The remaining error is the following:
/home/leio/dev/coreboot-v3/util/dtc/dtc-lexer.l: In function ‘yylex’:
/home/leio/dev/coreboot-v3/util/dtc/dtc-lexer.l:73: error: ‘yylval’ undeclared (first use in this function)
/home/leio/dev/coreboot-v3/util/dtc/dtc-lexer.l:73: error: (Each undeclared identifier is reported only once
/home/leio/dev/coreboot-v3/util/dtc/dtc-lexer.l:73: error: for each function it appears in.)
dtc-parser.tab.h doesn't seem to get an "extern YYSTYPE yylval" declaration, which per documentation should
only happen for pure parser cases ("%define api.pure"), but I can't find any such declaration in dtc to cause
the problem.
Note that upstream dtc builds fine with bison-2.4
Signed-off-by: Mart Raudsepp <mart.raudsepp@artecdesign.ee>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@1004 f3766cd6-281f-0410-b1cd-43a5c92072e9
Fix the issue. OBJ->SRC conversions are a bit tricky to get right.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@989 f3766cd6-281f-0410-b1cd-43a5c92072e9
table get rebuilt unconditionally due to slightly incorrect
dependencies.
That's wasteful and may hide other dependency bugs.
Fix the lar, lzma, nrv2b and option table dependencies.
This trims down recompilation time a lot. The only remaining stuff being
rebuilt is:
~/corebootv3-better_dependencies> make
CP build/config.h
GEN build/build.h
LAR build/coreboot.rom
PAYLOAD none (as specified by user)
CP build/bios.bin
DONE
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@984 f3766cd6-281f-0410-b1cd-43a5c92072e9
Signed-off-by: Ronald G. Minnich <rminnich@gmai.com>
Acked-by: Ronald G. Minnich <rminnich@gmai.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@970 f3766cd6-281f-0410-b1cd-43a5c92072e9
alue. There
is a known bug in v2/v3 wherein a BAR that is set is ignored. This change will c
ome in very
slowly as it is a bit tricky to get right as we redesign the dev code.
Also make the vm86 stuff use the SRC instead of OBJ names so we can see it in ks
cope.
Finally, beginnings of documentation changes, not finished yet.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@965 f3766cd6-281f-0410-b1cd-43a5c92072e9
1. moves the run_bios function down so it can call setup_realmode_idt
2. adds the __attribute__((regnum(0))) to biosint because it is called from assembly
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@964 f3766cd6-281f-0410-b1cd-43a5c92072e9
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@938 f3766cd6-281f-0410-b1cd-43a5c92072e9
I did change the /bin/bash to /bin/sh per the comments.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@919 f3766cd6-281f-0410-b1cd-43a5c92072e9
multiple links. The way this was done in v2 was a big confusing; this way is
less so.
The changes are easy. Getting them right has been hard :-)
First, for a k8 north that has three links, you can name each one as follows:
pci0@18,0
pci1@18,0
pci2@18,0
We have to have the same pcidevfn on these because that is how the k8 works.
But the unit numbers (pci0, pci1, etc.) distinguish them.
The dts will properly generate a "v3 device code"
compatible static tree that puts the links in the right place in the
data structure.
The changes to dts are trivial.
As before, dts nodes with children are understood to be a bridge.
But what if there is a dts entry like this:
pci1@18,0 {/config/("northbridge/amd/k8/pci");};
This entry has no children in the dts.
How does dt compiler know it is a bridge? It can not know unless
we add information to the dts for that northbridge part.
To ensure that all bridge devices are detected, we support the following:
if a dts node for a device has a bridge property, e.g.:
{
device_operations = "k8_ops";
bridge;
};
The dt compiler will treat it as a bridge whether it has children or not.
Why would a device not have children? Because it might be attached to a
pci or other socket, and we don't know at build time if the socket is empty,
or what might be in the socket.
This code has been tested on dbe62 and k8 simnow, and works on each.
It is minimal in size and it does what we need. I hope it resolves our
discussion for now. We might want to improve or change the device code
later but, at this point, forward motion is important -- I'm on a deadline for
a very important demo Oct. 22!
Also included in this patch are new debug prints in k8 north.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@865 f3766cd6-281f-0410-b1cd-43a5c92072e9
dtc only uses dev_fn as identifier for a PCI device. That gets us a name
collision if we have the same dev_fn combination on multiple buses.
Either we add a random unique ID to the struct name or we integrate the
path to the parent device as well.
I decided to go for integration of parent device path.
With the following device tree
/{
cpus {};
domain@0 {
bus@0 {
pci@0,0 {
};
pci@1,1 {
};
pci@f,0 {
bus@1 {
pci@0,0 {
};
};
};
};
};
};
we get the old names:
dev_root
dev_cpus
dev_domain_0
dev_bus_0
dev_pci_0_0
dev_pci_1_1
dev_pci_f_0
dev_bus_1
dev_pci_0_0 COLLISION!!!
and the new names:
dev_root
dev_cpus
dev_domain_0
dev_domain_0_bus_0
dev_domain_0_bus_0_pci_0_0
dev_domain_0_bus_0_pci_1_1
dev_domain_0_bus_0_pci_f_0
dev_domain_0_bus_0_pci_f_0_bus_1
dev_domain_0_bus_0_pci_f_0_bus_1_pci_0_0
Ron would like shorter names because they only have to be
machine-readable. That's left for another patch.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@860 f3766cd6-281f-0410-b1cd-43a5c92072e9
Fix the bus location for Qemu IDE.
This patch only provides the needed infrastructure for per-device
subsystem IDs, it does not hook them up to the PCI core yet, so this
patch is a no-op.
By the way, the on_mainboard property is activating lots of completely
untested code paths in v3, so someone might want to audit them.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@844 f3766cd6-281f-0410-b1cd-43a5c92072e9
Now to start testing.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@810 f3766cd6-281f-0410-b1cd-43a5c92072e9
few hardcodes introduced with my checker.
Tested on Linux and OSX.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@798 f3766cd6-281f-0410-b1cd-43a5c92072e9
simply hope they are unused/empty and will get runtime crashes/
corruption/malfunction if they are not empty. Same applies to any
sections with relocation entries which can not be resolved during
link time.
Check for the emptiness of these sections and abort the build on error.
This triggers on all stage1/initram global variables which are not
declared the right way. It also triggers on local static variables.
Features of this checker:
- It doesn't only check for non-empty .data and .bss, but also for
unknown sections which would be a problem.
- It gives you the offending filename, the section and the variable
name.
- It won't stop after the first error and will tell you about all errors
for a given file list.
This found a long-standing bug introduced in r729 and fixed in r786.
It also broke the build of every Geode target in the v3 tree because
they had multiple bugs. And it broke the build of the K8 code because
of a bug there.
Other fixes resulting from this checker are in r790 and r791.
Ron already fixed some of the bugs uncovered by this checker.
Tested for all possible variations of .data and .bss usage.
Sample output follows:
CC build/coreboot.initram (XIP)
CHECK initram (non-empty writable/allocatable sections)
build/coreboot.initram_partiallylinked.o: section .data: foo1
build/coreboot.initram_partiallylinked.o: section .bss: foo2
build/coreboot.initram_partiallylinked.o: section .data.rel.ro.local:
msrnames.2746
make: *** [build/coreboot.initram] Error 1
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Segher Boessenkool <segher@kernel.crashing.org>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@794 f3766cd6-281f-0410-b1cd-43a5c92072e9
