Due to some problems with PCI transactions, Geode LX needs the ROM cache properties to be write-serialize + cache disabled by runtime. More details below.
Add mainboard_pre_payload() call to each mainboard as the final coreboot function before the payload is called by stage1.
Note that this patch also grows the bootblock from 16K to 20K to make room for mainboard_pre_payload().
"The problem is a transaction depth issue and bottlenecks inside the GX
and LX that go across PCI. The conditions are very complicated but it
comes down to we need write serialization for writes to PCI. If you
look in the data book you can't have write serialization and the cache
enabled on a given area. During coreboot we don't have to worry about
a write or a PCI bus master so I think we can enable caching the ROM.
After coreboot we can't be sure what will happen in the system so we
need to set it up to be safe. For example flashrom just clears the
write protect bit. If the cache were enabled (no write serialization)
and flashrom was writing the ROM we would be in a precarious position.
A PCI bus master doing a read or a write that has a hit on a tag
would cause enough bottleneck conditions that it might hit the bug. We
could change flashrom but that doesn't help other tools. We need to
leave the system in a safe state. Also, caching the ROM after it is no
longer used doesn't make much sense. So, we need a call just before
the payload runs to clean up the system."
Signed-off-by: Marc Jones <marc.jones@amd.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@573 f3766cd6-281f-0410-b1cd-43a5c92072e9
- I left LB_TAG_ intact because they are used by the payloads
- file renames are still missing. see next commit
- some lb_ renames might be missing. feel free to provide patches.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@564 f3766cd6-281f-0410-b1cd-43a5c92072e9
_MAINOBJECT #defined. Calls from all other files ended up in nirvana
because the compiler was not able to calculate the address of the
wrapper for the absolute call. The linker tried, but failed miserably.
Use the -combine flag and compile all of initram at once. This enables
GCC to calculate the address of the abscall wrapper, resulting in
working code.
Segher Boessenkool thinks the patched code works only by accident
because GCC has no way to specify generation of XIP code. According to
him, future GCC versions or other circumstances may break the code.
While this patch makes code work for now, it does NOT check whether the
generated code tries to write to memory outside the stack (general
writable data). That will of course fail, but I hope porters are smart
enough to avoid that.
Corey Osgood writes:
Great work tracking this down! This is okay for now, but we need to look
for a better solution in the future. Counting on porters who may or may
not remember this discussion to avoid something isn't good
future-proofing.
Checking the ELF sections for read-write data and stopping the build
with an error could make this future-proof.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Corey Osgood <corey.osgood@gmail.com>
git-svn-id: svn://coreboot.org/repository/LinuxBIOSv3@537 f3766cd6-281f-0410-b1cd-43a5c92072e9
the x86 arch makefile. This makes porting to a new mainboard less
confusing.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/LinuxBIOSv3@529 f3766cd6-281f-0410-b1cd-43a5c92072e9
and create a valid LAR header with an entry value. This will fix the
problems Ron is having on the ALIX 1C and probably allow it to boot.
It also sets the text base of the .o to 0, instead of whatever wacky
value gld is choosing, so all platforms will have the same value.
Get away from worrying about potential gld bugs, now and in the future.
As added benefit, we obsolete a lot of code without introducing
new code.
Qemu target entry point debugging has been added to be able to spot
problems with entry points in the future.
This patch is a joint work of Ron and Carl-Daniel.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/LinuxBIOSv3@523 f3766cd6-281f-0410-b1cd-43a5c92072e9
Makefiles clean and simple.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://coreboot.org/repository/LinuxBIOSv3@517 f3766cd6-281f-0410-b1cd-43a5c92072e9
had _SHARED defined during compilation, each of them would contain an
assignment of stage0_printk to *printk. During linking, this caused
errors as multiple definitions of printk existed.
Make sure _SHARED alone gives you only the printk prototype, and iff
_MAINOBJECT is defined as well, include the assignment.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://coreboot.org/repository/LinuxBIOSv3@516 f3766cd6-281f-0410-b1cd-43a5c92072e9
probably be factored out together with the rest of the lines in
mainboard/* later, but for now it'll do.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/LinuxBIOSv3@515 f3766cd6-281f-0410-b1cd-43a5c92072e9
post_code.c (thus drop it from console.h).
Instead, have console.h #include post_code.h and drop other
explicit #includes of post_code.h in the code; console.h is already
included in pretty much every file.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
git-svn-id: svn://coreboot.org/repository/LinuxBIOSv3@513 f3766cd6-281f-0410-b1cd-43a5c92072e9
This fixes for example printk calls from initram code.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Jordan Crouse <jordan.crouse@amd.com>
git-svn-id: svn://coreboot.org/repository/LinuxBIOSv3@505 f3766cd6-281f-0410-b1cd-43a5c92072e9
* statically link linuxbios.initram for now (depends on printk, post_code
and die)
* greatly simplify all makefiles by creating a global Rules.make
* use $(dir $@) in Makefiles instead of absolute paths for mkdir..
* clean up Makefiles by calling components' code locally instead of in the
Makefile. (Remember: one day, no code per mainboard)
* unconditionally create .xcompile in case it changed
* add NM to xcompile
* create $(obj)/linuxbios.map with all symbols of all stages
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://coreboot.org/repository/LinuxBIOSv3@463 f3766cd6-281f-0410-b1cd-43a5c92072e9
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/LinuxBIOSv3@416 f3766cd6-281f-0410-b1cd-43a5c92072e9
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/LinuxBIOSv3@415 f3766cd6-281f-0410-b1cd-43a5c92072e9
all the early_*
stuff to stage1. All targets build and qemu boots.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://coreboot.org/repository/LinuxBIOSv3@414 f3766cd6-281f-0410-b1cd-43a5c92072e9
Get dbe61 initram into buildable shape. This depends
the msr_t patch which is in the pipeline.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/LinuxBIOSv3@395 f3766cd6-281f-0410-b1cd-43a5c92072e9
Acked-by: Stefan Reinauer <stepan@coresystems.de
This patch adds artec dbe61 support, removes all mainboard.c, and
adds
the code to dtc so that it takes these properties from the top level
dts:
/{
.
.
.
mainboard-vendor = "AMD";
mainboard-part-number = "Norwich";
}
statictree.h will have:
extern const char *mainboard_vendor, *mainboard_part_number;
and statictree.c will have:
const char *mainboard_vendor = "AMD";
const char *mainboard_part_number = "Norwich";
It is an error to NOT have the vendor and part number in the top
level dts.
thanks
ron
Get rid of mainboard.c in all mainboard directories.
Modify dtc so that it creates declarations (in statictree.h) and
generates the char *
for mainboard name and part # (in statictree.c).
Failure to set up a mainboard-vendor
OR mainboard-part-number property in the mainboard dts will get a
helpful and descriptive error message (tested).
This may be a first for the linuxbios config
tools.
Add Georgi's patch for the bug in flattree.c; assign *cp = 0.
git-svn-id: svn://coreboot.org/repository/LinuxBIOSv3@394 f3766cd6-281f-0410-b1cd-43a5c92072e9
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/LinuxBIOSv3@389 f3766cd6-281f-0410-b1cd-43a5c92072e9
NOTE: We're going to need to change the arch/x86 to have, e.g.,
arch/x86/geodelx. But we need to get lined up with the tree first.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://coreboot.org/repository/LinuxBIOSv3@381 f3766cd6-281f-0410-b1cd-43a5c92072e9
initram. Gets errors as we don't have ram support yet, working that
now.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://coreboot.org/repository/LinuxBIOSv3@354 f3766cd6-281f-0410-b1cd-43a5c92072e9
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Peter Stuge <peter@stuge.se>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://coreboot.org/repository/LinuxBIOSv3@325 f3766cd6-281f-0410-b1cd-43a5c92072e9
