This is a python script that does basically the same thing as the
rebase.sh script, but in the other direction. rebase.sh takes files
from the chromium tree (cros) and pulls them to the coreboot.org tree.
cborg2cros, as the name implies, updates patches to go into the cros
tree from coreboot.
It adds the 'UPSTREAM: ' identifier to the start of the commit message,
and uses the text '(cherry-picked from commit #####)' instead of
'Original-Commit-Id: #####'
It also adds the 'TEST=', 'BRANCH=', and 'BUG=' lines if they aren't
there.
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/15323
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Change-Id: Ibad9a5f0d0d2c713cf08e103c463e2e82768c436
Reviewed-on: https://chromium-review.googlesource.com/370698
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
3 out of 4 architectures currently zero out the payload BSS in early
assembly code, which is pointless since the code loading the payload has
already done that (with a more efficient memset). ARM64 has never had
any code like this and can run just fine without it. This also defeats
the new optimization of moving the heap out of the BSS, since all three
implementations assume that everything between _edata and _end is BSS.
We should just take this out.
BUG=None
BRANCH=None
TEST=None
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/16091
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Change-Id: I45cd2dabd94da43ff0f77e990f11c877cee6cda1
Reviewed-on: https://chromium-review.googlesource.com/370697
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
cbfs_get_handle() allocates memory for a handle and doesn't free it if
it errors out later, leaving the memory permanently leaked. Fix.
BUG=None
BRANCH=None
TEST=None
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/16207
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Change-Id: Ide198105ce3ad6237672ff152b4490c768909564
Reviewed-on: https://chromium-review.googlesource.com/369153
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
FSP unconditionally locks parts of the NVRAM in the RTC.
This change will enable coreboot to update the locking policy
and be able to unlock the region
BUG=chrome-os-partner:55944
BRANCH=None
TEST=Check 'crossystem dev_boot_usb=1'
Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com>
Reviewed-on: https://review.coreboot.org/16144
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Giri P Mudusuru <giri.p.mudusuru@intel.com>
Change-Id: I70fd2bafa6ff9eb9cdf284b9780e4b90dee0f4ce
Reviewed-on: https://chromium-review.googlesource.com/369150
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
In particular:
- Fix the condition of the loop that fills the mid-level page table
- Adhere to the format of sptbr
BUG=None
BRANCH=None
TEST=None
Signed-off-by: Jonathan Neuschfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/16120
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Change-Id: I575093445edfdf5a8f54b0f8622ff0e89f77ccec
Reviewed-on: https://chromium-review.googlesource.com/369148
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
I copied it from commit e10d2def7d of spike and made sure the copyright
header is still there.
BUG=None
BRANCH=None
TEST=None
Signed-off-by: Jonathan Neuschfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/15832
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Change-Id: Ie8b56cd2f4855b97d36a112a195866f4ff0feec5
Reviewed-on: https://chromium-review.googlesource.com/369147
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Add GPIOs initialisation before dock check.
Needed in order to properly detect the presence or absence of the lenovo
dock.
Previously the check always reported the dock as connected and currently
it always reports it as disconnected since the GPIOs are not properly
initialised during the check.
Tested and confirmed working.
BUG=None
BRANCH=None
TEST=None
Signed-off-by: Antonello Dettori <dev@dettori.io>
Reviewed-on: https://review.coreboot.org/16139
Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
Reviewed-by: Kysti Mlkki <kyosti.malkki@gmail.com>
Change-Id: I7fbf8c2262a1eb5dee9cbe5e23bf44f7f8181009
Reviewed-on: https://chromium-review.googlesource.com/369145
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
It was a band-aid that isn't required any more.
BUG=None
BRANCH=None
TEST=None
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: https://review.coreboot.org/16142
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Change-Id: Ib1793ae8fe25eecf9bd5ab8e5feef0d9380b43c2
Reviewed-on: https://chromium-review.googlesource.com/369142
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
To override fallback/foo's position or alignment in region BAR, use
fallback/foo-BAR-{position,align} = 0x1234
Like for the global settings, specifying both isn't allowed
because that's rather pointless.
BUG=None
BRANCH=None
TEST=None
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: https://review.coreboot.org/16140
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Change-Id: I94f41ebc9f35108267265df4164f23b70e3d0bf6
Reviewed-on: https://chromium-review.googlesource.com/369140
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
They're now sorted later in the process after the per-region file lists
are determined.
BUG=None
BRANCH=None
TEST=None
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: https://review.coreboot.org/16138
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Change-Id: I0bba381d09dc4b99e2fe5cae16ff7ffcb5b3aa82
Reviewed-on: https://chromium-review.googlesource.com/369099
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Make sure that files with a fixed position are placed first (whose order
doesn't matter: either they collide or they don't), then all aligned
files (where we just hope that the right thing happens) and finally the
files with no further requirements (again, hope).
It's still a pretty good heuristic given a typical coreboot image.
The global sorting that happens earlier in the build flow will be
removed in the future to make room for per-region requirements.
BUG=None
BRANCH=None
TEST=None
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: https://review.coreboot.org/16137
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Change-Id: I269c00b2ece262c95d310b76a6651c9574badb58
Reviewed-on: https://chromium-review.googlesource.com/369098
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Set default value for UART port
BUG=chrome-os-partner:51844
BRANCH=None
TEST=Boot to chrome and check console
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-on: https://review.coreboot.org/16133
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Change-Id: I5e76066e0ff531303595dcd5a99f2f8db379e89b
Reviewed-on: https://chromium-review.googlesource.com/369095
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This patch enables serial debug functionality for ASL code based on
UART type(legacy/LPSS).
From Skylake onwards all Intel platform uses LPSS based UART for serial
console hence provide option to redirect ASL log over LPSS UART.
Example:
Name (OBJ, 0x12)
APRT (OBJ)
APRT ("CORE BOOT")
Output:
0x12
CORE BOOT
BUG=none
BRANCH=none
TEST=Built and boot kunimitsu to ensure to be able to get ASL console log.
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/16070
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Change-Id: I18c65654b8eb1ac27af1f283d413376fd79d47db
Reviewed-on: https://chromium-review.googlesource.com/369120
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
When booting Linux as a coreboot payload, serial access does not work
properly. This is because the setup code erroneously sets IRQ3 and
IRQ4 to level. The UART on Broadwell is 8250/16550 compatible, thus
ISA and edge-triggered.
This change is not necessary on the non-FSP version of Broadwell support.
The non-FSP version does not set these IRQ overrides.
Fix verified booting Linux 4.6.0-rc2 on Intel Camelback Mountain CRB,
using Intel FSP 1.0.
BUG=None
BRANCH=None
TEST=None
Signed-off-by: Kevin Paul Herbert <kevin@trippers.org>
Reviewed-on: https://review.coreboot.org/16065
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Change-Id: I17b466676e7f4891c3e75ce6208e1580c9eaf742
Reviewed-on: https://chromium-review.googlesource.com/369119
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
On some kind of terms (shell in emacs), the color-ctrl
letters don't work. The backspaces can not delete
correct number of letters. So we don't print color-ctrl
letters in loop.
BUG=None
BRANCH=None
TEST=None
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/16066
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Change-Id: I1f1729095e8968a9344ed9f1f278f7c78f7110e9
Reviewed-on: https://chromium-review.googlesource.com/369118
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Prior to this patch, time->wday was not being initialized in rtc_get(),
but was still being used by rtc_display() to print a day.
Set to -1 which gets printed as "unknown ".
Fixes coverity issue 1357459 - Uninitialized scalar variable
BUG=None
BRANCH=None
TEST=None
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/15899
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Change-Id: Idecb7968f854df997b58a342e1a06a879f299394
Reviewed-on: https://chromium-review.googlesource.com/369117
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Switch from passing FSP the serial port address to passing FSP the
serial port output routine. This enables coreboot to use any UART in
the system and also log the FSP output.
TEST=Build and run on Galileo Gen2
BUG=None
BRANCH=None
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/16105
Reviewed-by: Martin Roth <martinroth@google.com>
Change-Id: I67d820ea0360a3188480455dd2595be7f2debd5c
Reviewed-on: https://chromium-review.googlesource.com/369116
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Add fsp_write_line function which may be called by FSP to output debug
serial data to the console.
TEST=Build and run on Galileo Gen2
BUG=None
BRANCH=None
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/16129
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Change-Id: If7bfcea1af82209dcdc5a9f9f2d9334842c1595e
Reviewed-on: https://chromium-review.googlesource.com/369115
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Add fsp_write_line function which may be called by FSP to output debug
serial data to the console.
TEST=Build and run on Galileo Gen2
BUG=None
BRANCH=None
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/16128
Reviewed-by: Martin Roth <martinroth@google.com>
Change-Id: Ib01aef448798e47ac613b38eb20bf25537b9221f
Reviewed-on: https://chromium-review.googlesource.com/369114
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Add write line routine which is called indirectly by FSP.
TEST=Build and run on Galileo Gen2.
BUG=None
BRANCH=None
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/16127
Reviewed-by: Martin Roth <martinroth@google.com>
Change-Id: Idefb6e9ebe5a2b614055dabddc1882bfa3bba673
Reviewed-on: https://chromium-review.googlesource.com/369113
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Instead of adding each file in all requested regions, sort by region,
then by file.
This is in preparation of per-region file options
(eg. position, alignment)
BUG=None
BRANCH=None
TEST=None
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: https://review.coreboot.org/16130
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
Change-Id: Ide09a1c8840279380294a059bbd5d2f9f0cba780
Reviewed-on: https://chromium-review.googlesource.com/369112
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
If some error happens in cbfs_payload_make_elf, the code jumps to "out",
and elf_writer_destroy(ew) is called. This may happen before an elf
writer is allocated.
To avoid accessing an uninitialized pointer, initialize ew to NULL;
elf_writer_destroy will perform no action in this case.
BUG=None
BRANCH=None
TEST=None
Signed-off-by: Jonathan Neuschfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/16124
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Change-Id: I5f1f9c4d37f2bdeaaeeca7a15720c7b4c963d953
Reviewed-on: https://chromium-review.googlesource.com/369111
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Minor change - Instead of stripping the quotes from CONFIG_DEVICETREE
inline, add it to the location where we normalize all the other Kconfig
variables.
BUG=None
BRANCH=None
TEST=None
Signed-off-by: Martin Roth <martinroth@chromium.org>
Reviewed-on: https://review.coreboot.org/16116
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Change-Id: Idbc58179c7b45160afef7d7e44f9b3b334f8c4a7
Reviewed-on: https://chromium-review.googlesource.com/368949
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This patch adds mainboard_smi_gpi_handler which handles the
SMI event. This can happen in situations like lidclose and
system goes to shutdown.
BUG=chrome-os-partner:54977
BRANCH=None
TEST=When system is in firmware mode executing the command
lidclose from ec console shuts down the system.
Signed-off-by: Shaunak Saha <shaunak.saha@intel.com>
Reviewed-on: https://review.coreboot.org/15834
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Change-Id: I8ff6001e48dcbbd4cee5097e759352d8fea6189b
Reviewed-on: https://chromium-review.googlesource.com/368948
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
GPIOs which trigger SMIs set the GPIO_SMI_STS status bits in SMI_STS
register. This patch also sets the SMI_EN bit in enable register for
each community based on GPIOROUTSMI bit in gpio pad. When SMI on a
gpio happens status needs to be gathered on gpio number which is done
by reading the GPI_SMI_STS and GPI_SMI_EN registers.
BUG=chrome-os-partner:54977
BRANCH=None
TEST=When system is in firmware mode executing the command
lidclose from ec console shuts down the system.
Signed-off-by: Shaunak Saha <shaunak.saha@intel.com>
Reviewed-on: https://review.coreboot.org/15833
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Change-Id: Id89a526106d1989c2bd3416ab81913e6cf743d17
Reviewed-on: https://chromium-review.googlesource.com/368947
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Commit 0d9cd92e (chromeos: Clean up elog handling) removed the
individual elog_init() calls from mainboards that did them and automated
adding certain events through the boot state machine. Unfortunately,
the new code would sometimes not log any specific event at all, and
thereby also never call elog_init() (through elog_add_event()) which
adds the "System boot" event.
We can assume that any board that configures the eventlog at all
actually wants to use it, so let's just add another call to elog_init()
to the boot state machine so we can ensure it gets called at least once.
BRANCH=None
BUG=chrome-os-partner:56001
TEST=Booted Kevin, confirmed that eventlog code runs again.
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/16118
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Change-Id: Ibe7bfc94b3e3d11ba881399a39f9915991c89d8c
Reviewed-on: https://chromium-review.googlesource.com/368946
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Instead of relying on global state to determine if an error
occurred provide the ability to know if an add or shrink
operation is successful. Now the call chains report the
error back up the stack and out to the callers.
BUG=chrome-os-partner:55932
BRANCH=None
TEST=None
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/16104
Reviewed-by: Furquan Shaikh <furquan@google.com>
Change-Id: Id4ed4d93e331f1bf16e038df69ef067446d00102
Reviewed-on: https://chromium-review.googlesource.com/369087
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Don't conditionally compile parts of the code. The unused pieces
get culled by the linker, and the #if's just clutter things up.
BUG=chrome-os-partner:55932
BRANCH=None
TEST=None
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/16102
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Change-Id: Ic18b2deb0cfef7167c05f0a641eae2f4cdc848ee
Reviewed-on: https://chromium-review.googlesource.com/369086
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
There were checks against global variables trying to determine
failing cases of elog_find_flash(). Instead move the checks
into elog_find_flash() and return value indicating failure.
A minimum 4KiB check was added to ensure the eventlog is at
least that size which makes the heuristic checks cleaner.
BUG=chrome-os-partner:55932
BRANCH=None
TEST=None
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/16101
Reviewed-by: Martin Roth <martinroth@google.com>
Change-Id: I4d9d13148555e05d4f217a10f995831a0e437fc3
Reviewed-on: https://chromium-review.googlesource.com/369085
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
There were 3 variables indicating the state of the event log
region. However, there's no need to keep track of those
individually. The only thing required is to know is if
elog_scan_flash() failed. There's no other tracking required
beyond that.
BUG=chrome-os-partner:55932
BRANCH=None
TEST=None
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/16100
Reviewed-by: Martin Roth <martinroth@google.com>
Change-Id: I88ad32091d3c37966a2ac6272f8ad95bcc8c4270
Reviewed-on: https://chromium-review.googlesource.com/369084
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
There were multiple paths where writes and erases of the flash
were being done. Instead provide a single place for synchronizing
the non-volatile storage from the mirrored event log. This
synchronization point resides as the very last thing done when
adding an event to the log. The shrinking check happens before
committing the event to non-volatile storage so there's no need
to attempt a shrink in elog_init() because any previous events
committed already honored the full threshold.
BUG=chrome-os-partner:55932
BRANCH=None
TEST=None
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/16099
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Change-Id: Iaec9480eb3116fdc2f823c25d028a4cfb65a6eaf
Reviewed-on: https://chromium-review.googlesource.com/369083
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This adds a cmos.layout and a cmos.default to ga-g41m-es2l.
This allows to set things like baud_rate, debug_level, etc.
from cmos.
BUG=None
BRANCH=None
TEST=None
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/15493
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Change-Id: I25df7a1f3a0ce486b96cfe05bda628f604b0baec
Reviewed-on: https://chromium-review.googlesource.com/369080
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This allows to set the preallocated memory for the IGD on x4x
using a cmos option.
If no cmos option is found a default value of 64M is used.
TESTED most options on ga-g41m-es2l with 2G dimm in one slot and 2x2G.
352M also works in contrast with gm45 where it is known to cause issues
with certain ram combinations.
BUG=None
BRANCH=None
TEST=None
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/15492
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Change-Id: I9051d080be82f6dfab37d353252e29b2ed1fca7f
Reviewed-on: https://chromium-review.googlesource.com/368889
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
The Intel documtentation, "Intel 4 Series Chipset Family"
mentions the possibility of 1, 4, 8 and 16M of preallocated
memory for the IGD, but does not document this.
This allows to set those undocumented values.
TESTED on ga-g41m-es2l with 2G dimm in one slot and 2x2G.
BUG=None
BRANCH=None
TEST=None
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/15491
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Change-Id: I92beb8d78907d4514a5aaf69248dd607dcf227c0
Reviewed-on: https://chromium-review.googlesource.com/368888
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This moves the Kconfig from the Super I/O manufacturer folder
to the chip folder instead.
This makes new chip commits self-contained unit as
edits to the central Kconfig file are no longer required.
BUG=None
BRANCH=None
TEST=None
Signed-off-by: Omar Pakker <omarpakker+coreboot@gmail.com>
Reviewed-on: https://review.coreboot.org/15973
Reviewed-by: Idwer Vollering <vidwer@gmail.com>
Change-Id: I7aee07919f2ae9204850c669e0ed3cb17d4de8cd
Reviewed-on: https://chromium-review.googlesource.com/368886
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Upstream proposed and merged a patch fixing the ARM Trusted Firmware
build issue that occurs with recent version sof binutils. This includes
this patch instead of the previous one.
See binutils commit 7ea12e5c3ad54da440c08f32da09534e63e515ca:
"Fix the generation of alignment frags in code sections for AArch64."
The issue was reported at:
https://sourceware.org/bugzilla/show_bug.cgi?id=20364
BUG=None
BRANCH=None
TEST=None
Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
Reviewed-on: https://review.coreboot.org/16110
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Change-Id: I16a8043d3562107b8e84e93d3f3d768d26dac7e4
Reviewed-on: https://chromium-review.googlesource.com/368885
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
