Fix bug detected by coverity to handle the zero capacity case. Specific
changes:
* Reduce loop count by one to handle zero capacity case
* Use structure instead of dual arrays
* Move structures into display_capacity routine
Coverity Issues:
* 1374931
* 1374932
* 1374933
* 1374934
TEST=Build and run on Galileo Gen2
Change-Id: I4784d261fbaaf707f3782a32993c1eca01944d15
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: bf5d5093fc
Original-Change-Id: Ie5c96e78417b667438a00ee22c70894a00d13291
Original-Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com>
Original-Reviewed-on: https://review.coreboot.org/19643
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/506171
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
s230u seems only have two sata ports: one for the 2.5in hdd and one for
msata. map 0x11 (port 0 & 4) enables hdd but not msata, and map 0x5
(port 0 & 2) enables both.
BUG=none
BRANCH=none
TEST=none
Change-Id: I11aba1d95e53ffc8e97c152bf6aa6b01d299820f
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 72f730e23c
Original-Change-Id: I1e9e96f0d0849b1e8c4e02aa4f686ceb5e10b3ab
Original-Signed-off-by: Bill XIE <persmule@gmail.com>
Original-Reviewed-on: https://review.coreboot.org/19523
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
Reviewed-on: https://chromium-review.googlesource.com/506170
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Remove unused field in generic SD/MMC controller data structure.
TEST=Build and run on Galileo Gen2
Change-Id: Icc3b0a6856e6454a2db45cf44cf01e3c2dada95e
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 1c1c071b88
Original-Change-Id: I7169dca07509a6f2513d62b593742daf764010b2
Original-Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com>
Original-Reviewed-on: https://review.coreboot.org/19629
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://chromium-review.googlesource.com/506169
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Is only present on the P45 subtype of chipset.
BUG=none
BRANCH=none
TEST=none
Change-Id: Iac30ec9f12a559730bf3e786301d7f5882caff52
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 293445ae1f
Original-Change-Id: I6b138db6654c83c40b5ca4b65d6ccd51ad4277fa
Original-Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Original-Reviewed-on: https://review.coreboot.org/18516
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://chromium-review.googlesource.com/506168
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
The coreboot had no supported the different frequency for gru yet.
e.g:
we can't support the bob to run ddr 800M for rev3 board and
run 928M for rev4 board.
So, in order to support the 800M and 928M ddr frequency for bob different
boards. We will use the ram_id and board_id to select the board on bob.
BRANCH=none
BUG=b:36666655
TEST=boot from bob, tested with memtester/s2r/reboot on bob.
Change-Id: I613050292a09ff56f4636d7af285075e32259ef4
Original-Change-Id: I613050292a09ff56f4636d7af285075e32259ef4
Original-Signed-off-by: Caesar Wang <wxt@rock-chips.com>
Original-Reviewed-on: https://review.coreboot.org/19558
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/488421
Commit-Ready: Caesar Wang <wxt@rock-chips.com>
Tested-by: Caesar Wang <wxt@rock-chips.com>
Reviewed-by: Philip Chen <philipchen@chromium.org>
Spread Spectrum Modulator (SSMOD) is a fully-digital circuit used to
modulate the frequency of the Silicon Creations Fractional PLL in order
to reduce EMI.
We need to turn the DPLL spread spectrum feature on to
reduce the EMI noise for DDR on bob.
BRANCH=none
BUG=b:37262721
TEST=mem checks the register value on bob.
localhost / # mem r 0xff76004c ---> 0x00000100
localhost / # mem r 0xff760050 ---> 0x00000860
TEST=Tested with memtester/s2r/reboot on bob.
Change-Id: I75461d4235bcf55324e6664a1220754e770b4786
Original-Change-Id: I75461d4235bcf55324e6664a1220754e770b4786
Original-Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
Original-Signed-off-by: Caesar Wang <wxt@rock-chips.com>
Original-Reviewed-on: https://review.coreboot.org/19557
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/377691
Commit-Ready: Caesar Wang <wxt@rock-chips.com>
Tested-by: Caesar Wang <wxt@rock-chips.com>
Reviewed-by: Philip Chen <philipchen@chromium.org>
Tested against a lenovo-manufactured tpm 1.2 module:
a /dev/tpm0 visible inside GNU/Linux, but there is no menu items in
SeaBIOS' interface, which seems a common issue of SeaBIOS on ivb boards.
BUG=none
BRANCH=none
TEST=none
Change-Id: I81485ce4f64e0e58a3204052a314cf20c6eaa439
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 6dcb789da9
Original-Change-Id: Id0dee74d945bae5d77eb669d8b9d468a67aee508
Original-Signed-off-by: Bill XIE <persmule@gmail.com>
Original-Reviewed-on: https://review.coreboot.org/19521
Original-Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-on: https://chromium-review.googlesource.com/501164
This replaces the custom environment controller handling in the it8728
driver with the common library.
It also updates the two existing boards with hwm register settings in
their devicetree config so they better match their vendor BIOS fan
control settings.
BUG=none
BRANCH=none
TEST=none
Change-Id: I200629a1d69e39ba9b5f7fdb9801fc4df5c320e5
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 1f064d7551
Original-Change-Id: Idf0c8908ba5ad6ff552b8302bffc638aa9052941
Original-Signed-off-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de>
Original-Reviewed-on: https://review.coreboot.org/19293
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://chromium-review.googlesource.com/501163
BUG=None
TEST=emerge-sand coreboot chromeos-bootimage and verify the keyboard
backlight can be bright and alt+f6, alt+f7 function keys can be used.
Change-Id: I9b70609a74d70856fc3aa72250f9ff1bc240af0b
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 709bc6eada
Original-Change-Id: I86a35551a9348ff6ad26dfccd3b2786282d56069
Original-Signed-off-by: Katherine Hsieh <Katherine.Hsieh@quantatw.com>
Original-Reviewed-on: https://review.coreboot.org/19479
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/501158
According to "Intel 4 Series Chipset Family datasheet" in the
description about GGC and DEVEN, CAPID0 bit46 is said to reflect the
presence of an internal graphic device. This would allow the P43 and
P45 chipset variants to work.
BUG=none
BRANCH=none
TEST=none
Change-Id: Ic71a7c81d494e91f4aee97fe489a4df29b99843f
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 5e3cb72a71
Original-Change-Id: Icdaa2862f82000de6d51278098365c63b7719f7f
Original-Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Original-Reviewed-on: https://review.coreboot.org/18515
Original-Reviewed-by: Nico Huber <nico.h@gmx.de>
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-on: https://chromium-review.googlesource.com/501157
The NGI writes to legacy VGA registers which should not happen when
VGA cycles are assigned to a different device.
TESTED on ga-g41m-es2l
BUG=none
BRANCH=none
TEST=none
Change-Id: Ibd9669589a05f5ec776c3f9bc81de65266ced83e
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 2e7efe65a2
Original-Change-Id: I0a03e35c0d7f2532edd6cc5e62d1cf07dab57f60
Original-Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Original-Reviewed-on: https://review.coreboot.org/19607
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Original-Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://chromium-review.googlesource.com/501156
This disables VGA cycles on IGD when an external VGA device is
found. This allows PCI or PCIe devices to be the 'main' VGA device if
found, while the IGD is still available.
TESTED on ga-g41m-es2l: SeaBIOS shows payload on external GPU while
linux (4.10) can use both as a framebuffer simultaneously without any
extra configuration.
BUG=none
BRANCH=none
TEST=none
Change-Id: I31fa03ca83a31ec741bd0dff3c4cffe57021581d
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: c80748c2d0
Original-Change-Id: I74890918feb0f1ff6b971c4aaa96f1f7b75266ac
Original-Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Original-Reviewed-on: https://review.coreboot.org/18504
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Nico Huber <nico.h@gmx.de>
Original-Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://chromium-review.googlesource.com/501155
Computes TSEG size dynamically.
Changes the size of legacy hole to match other Intel northbirdges.
Refactor this a little by needing one less variable.
BUG=none
BRANCH=none
TEST=none
Change-Id: I71eccc97aee616652c992d87753c54a60fd1c023
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 4c4f56a6ba
Original-Change-Id: I0e6898c06a2bc1016eeaa3f002ff6c39657018ae
Original-Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Original-Reviewed-on: https://review.coreboot.org/18511
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://chromium-review.googlesource.com/501154
Change a4b11e5c90 (soc/intel/skylake: Perform CPU MP Init
before FSP-S Init) dropped mtrr_check while re-organizing
code. Add the check back after MTRR setup is performed.
BUG=b:36656098
TEST=Verified that MTRR check is done after setup on poppy.
Change-Id: If2f00fa65c716036bd5da37b9ba150460350cfbc
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: e411f8eb72
Original-Change-Id: I440405c58c470ffa338be386d84870635530a031
Original-Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/19609
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Philippe Mathieu-Daud <philippe.mathieu.daude@gmail.com>
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/501153
Configure the SD controller to handle the SD card slot.
* Galileo supports a removable SD card slot.
* Set SD card initialization frequency to 100 MHz.
* Set default removable delays.
* Build SD/MMC components by default
TEST=Build and run on Galileo Gen2
Change-Id: Icb6ca60d4f7ca9e7f6b387c622f7417713a2f9c7
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 1ea7cce8ae
Original-Change-Id: Iaf4faa40fe01eca98abffa2681f61fd8e059f0c4
Original-Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Original-Reviewed-on: https://review.coreboot.org/19212
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://chromium-review.googlesource.com/501152
With change a4b11e5c90 (soc/intel/skylake: Perform CPU MP Init
before FSP-S Init) to perform CPU MP init before FSP-S init, MTRR
programming was moved to be performed after CPU init is done. However,
in order to allow callbacks after MP init, PARALLEL_MP_AP_WORK needs
to be enabled. Since this option was not selected, MTRR programming
always failed in ramstage for Skylake / Kaby Lake mainboards.
BUG=b:36656098
TEST=Verified 2500+ cycles of suspend resume on poppy.
Change-Id: I1ca205254163b692221ad9178ddb9317e2731387
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: a585358f9b
Original-Change-Id: I22a8f6ac90ba35075ff97dd57bab66c129f3e771
Original-Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/19608
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/501151
The SD/MMC test support consists of:
* Add Kconfig value to enable the SD/MMC test support.
* Add Kconfig value to enable the logging support.
* Add SD/MMC controller init code and read block 0 from each partition.
* Add logging code to snapshot the transactions with the SD/MMC device.
* Add eMMC driver for ramstage to call test code.
* Add romstage code to call test code.
* Add bootblock code to call test code.
TEST=Build and run on Galileo Gen2
Change-Id: Id81621f1b40d95b8f8b48b396e38ec3912d17d9f
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 16bc9bab2a
Original-Change-Id: I72785f0dcd466c05c1385cef166731219b583551
Original-Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Original-Reviewed-on: https://review.coreboot.org/19211
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://chromium-review.googlesource.com/501150
This code ought not to run if ME is disabled. It also prohibits
writing to some GMCH regs like GGC bit1.
Intel 4 Series Chipset Family datasheet refers to this as
"ME stolen Memory lock" without actually describing this
functionality.
BUG=none
BRANCH=none
TEST=none
Change-Id: I2515e965aafbac95e78eef9a42ce10c302c892d7
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: ddc8828697
Original-Change-Id: Iaa8646e535e13c44c010ccd434a5af954cf7dfbc
Original-Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Original-Reviewed-on: https://review.coreboot.org/18513
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://chromium-review.googlesource.com/501147
This reverts commit 952d9af2ed.
I need to do an Eve BIOS release and this cannot be present yet as it
has to be released at the same time as the new touchpad firmware.
BUG=b:35581264
BRANCH=none
TEST=none
Change-Id: I35da873b5f071e803688ff8ccf08274303b8f228
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://chromium-review.googlesource.com/498587
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Provide a failing get_wifi_sar_limits() to allow SAR Kconfig
options to be selected without relying on CHROMEOS which currently
has the only code to provide SAR data.
BUG=none
BRANCH=none
TEST=none
Change-Id: I7f4de5de4bc3919de2a7236bf0dc8c41841634bf
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 2abbbf1503
Original-Change-Id: I1288871769014f4c4168da00952a1c563015de33
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/19580
Original-Reviewed-by: Furquan Shaikh <furquan@google.com>
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-on: https://chromium-review.googlesource.com/498348
Use `uintptr_t` instead of `uint32_t`, fixing the error below on 64-bit
systems, where pointers are 64-bit wide.
```
cc -O0 -g -Wall -W -Wno-unused-parameter -Wno-unused-but-set-variable -Wno-sign-compare -Wno-unused-function -c -o intelmetool.o intelmetool.c
intelmetool.c: In function dump_me_memory:
intelmetool.c:85:45: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast]
dump = map_physical_exact((off_t)me_clone, (void *)me_clone, 0x2000000);
^
```
BUG=https://ticket.coreboot.org/issues/111
Change-Id: I89c28fe9a3c5da1b2d5cad802624228680519567
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 57d912bacc
Original-Change-Id: Id8d778e97090668ad9308a82b44c6b2b599fd6c3
Original-Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Original-Reviewed-on: https://review.coreboot.org/19567
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Original-Reviewed-by: Philippe Mathieu-Daud <philippe.mathieu.daude@gmail.com>
Original-Reviewed-by: Paul Wise (Debian) <pabs@debian.org>
Reviewed-on: https://chromium-review.googlesource.com/498325
The device ids changed names between patches. Fix them to
not break the build any more.
BUG=none
BRANCH=none
TEST=none
Change-Id: I5e4a2522e45c5aa60db90b53aa7fd7c9b61bd572
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: f27d98fadc
Original-Change-Id: I1d74d95ec6b516c4d8354a714b2b302557743fe0
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/19600
Original-Reviewed-by: Furquan Shaikh <furquan@google.com>
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://chromium-review.googlesource.com/498324
spi_crop_chunk is a property of the SPI controller since it depends
upon the maximum transfer size that is supported by the
controller. Also, it is possible to implement this within spi-generic
layer by obtaining following parameters from the controller:
1. max_xfer_size: Maximum transfer size supported by the controller
(Size of 0 indicates invalid size, and unlimited transfer size is
indicated by UINT32_MAX.)
2. deduct_cmd_len: Whether cmd_len needs to be deducted from the
max_xfer_size to determine max data size that can be
transferred. (This is used by the amd boards.)
BUG=none
BRANCH=none
TEST=none
Change-Id: Iae7e196ab1e3fc1a665a4d27e722b920e78e8fd8
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: de705fa1f4
Original-Change-Id: I81c199413f879c664682088e93bfa3f91c6a46e5
Original-Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/19386
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Tested-by: coreboot org <coreboot.org@gmail.com>
Reviewed-on: https://chromium-review.googlesource.com/498323
Now that we have a common block driver for fast spi flash controller,
provide spi_ctrlr structure that can be used by different platforms
for defining the bus-ctrlr mapping. Only cs 0 is considered valid.
BUG=none
BRANCH=none
TEST=none
Change-Id: Ib4bf50bc9e72465e59aa82d1ca76f7e731bc8f2b
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: f1db5fdb4d
Original-Change-Id: I7228ae885018d1e23e6e80dd8ce227b0d99d84a6
Original-Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/19575
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-on: https://chromium-review.googlesource.com/498322
tis_close() must be called after tis_open() otherwise the locked
locality isn't released and the sessions hangs.
Tested=PC Engines APU2
BUG=none
BRANCH=none
TEST=none
Change-Id: Idd14621de1685ac965e96ba8b05365b829690e10
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 35418f9814
Original-Change-Id: I1a06f6a29015708e4bc1de6e6678827c28b84e98
Original-Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org>
Original-Reviewed-on: https://review.coreboot.org/19535
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://chromium-review.googlesource.com/498321
The AP sends the Cr50 a request to enable the new firmware image. If
the new Cr50 image was found and enabled, the AP expects the Cr50 to
reset the device in 1 second.
While waiting for the Cr50 to reset, the AP logs a newly defined event
and optionally shuts down the system. By default the x86 systems power
off as shutting those systems down is not board specific.
BRANCH=gru,reef
BUG=b:35580805
TEST=built a reef image, observed that in case cr50 image is updated,
after the next reboot the AP stops booting before loading depthcharge,
reports upcoming reset and waits for it.
Once the system is booted after that, the new event can be found
in the log:
localhost ~ # mosys eventlog list
...
7 | 2017-03-23 18:42:12 | Chrome OS Developer Mode
8 | 2017-03-23 18:42:13 | Unknown | 0xac
9 | 2017-03-23 18:42:21 | System boot | 46
...
Change-Id: I12706aebb64d6fb6b53386d8e9379b5781a7a84e
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: b9126fe46c
Original-Change-Id: I45fd6058c03f32ff8edccd56ca2aa5359d9b21b1
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/18946
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://chromium-review.googlesource.com/498315
Provide a common function to issue reboot commands to the EC.
Expose that function for external use and use it internal to
the module.
BUG=b:35580805
Change-Id: Ia0668359af2bb9acd0ad5c9086b63dcd3228e926
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: e68d22fbbc
Original-Change-Id: I1458bd7119b0df626a043ff3806c15ffb5446c9a
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/19573
Original-Reviewed-by: Furquan Shaikh <furquan@google.com>
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/498313
Use register name instead of hex values.
No functional change.
BUG=none
BRANCH=none
TEST=none
Change-Id: If7cb7a02841f960f547eaba62f9455499f6ad593
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: c368620d60
Original-Change-Id: I08fc8435f29ab87a0534946b0e0c43231919785d
Original-Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Original-Reviewed-on: https://review.coreboot.org/19545
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/498310
Use register name instead of hex value.
No functional change.
BUG=none
BRANCH=none
TEST=none
Change-Id: I3ed947b8d353083053e801d555239f2805bfe717
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 5c31af8e1a
Original-Change-Id: Iacfe609f6454e6d58c9733f425377464238ce4a9
Original-Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Original-Reviewed-on: https://review.coreboot.org/19544
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/498309
This patch adds the eMMC as one of the thermal sensor under DPTF.
Also, updates few comments for better interpretation and mapping.
BUG=None
BRANCH=None
TEST=Built for poppy.
Change-Id: I22edad5afd0e24fd19ee7857b750f0168d13a818
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: c9026b2945
Original-Change-Id: I6d05bb7a2f857dc5bc98227c8327b2ff1bd5b913
Original-Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Original-Reviewed-on: https://review.coreboot.org/19524
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/498308
Update the DPTF parameters based on thermal test result.
1. Update DPTF CPU/TSR0/TSR1/TSR2 passive/critial trigger points.
CPU passive point:83, critial point:99
TSR0 passive point:60, critial point:70
TSR1 passive point:50, critial point:90
TSR2 passive point:77, critial point:90
2. Update PL1/PL2 Min Power Limit/Max Power Limit
Set PL1 min to 4W, max to 12W, and step size to 0.2W
3. Change thermal relationship table (TRT) setting.
Change CPU Throttle Effect on CPU sample rate to 5secs
Change CPU Effect on Temp Sensor 0 sample rate to 60secs
The TRT of TCHG is TSR1, but real sensor is TSR2. sample rate to 30secs
Change Charger Effect on Temp Sensor 2 sample rate to 30secs
Change CPU Effect on Temp Sensor 2 sample rate to 120secs
BUG=None
TEST=build and boot on electro dut
Change-Id: I4488a6d4abbf90f34e5f7174ab71a6e62c5cb996
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 8caf8a23f9
Original-Change-Id: I0ea0bab7fa6b0ad75d9ddacbd7cd882f91e4b0db
Original-Signed-off-by: Katherine Hsieh <Katherine.Hsieh@quantatw.com>
Original-Reviewed-on: https://review.coreboot.org/19538
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/498307
NR indicates the last non empty region, which in this case is
GbE (region3). Needed for flashrom ifd layout support.
BUG=none
BRANCH=none
TEST=none
Change-Id: I981ff184dd4e8a88aaa103117d8c3991c08cc878
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 915a4cadf4
Original-Change-Id: I3f4dcb0d41718dd176982679f8e045681fd3f486
Original-Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Original-Reviewed-on: https://review.coreboot.org/19565
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Nico Huber <nico.h@gmx.de>
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://chromium-review.googlesource.com/497405
The current implementation is incorrect and is
actually disabling the ports. Fixes that.
BUG=b:37486021, b:35775024
BRANCH=None
TEST=reboot and ensure that we can boot from
SATA SSD.
Change-Id: I908c1ab04b6d5fd823a89bf1a1eae3116920e468
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: d44d028050
Original-Change-Id: I8525f6f5ddfdf61c564febd86b1ba2e01c22d9e5
Original-Signed-off-by: Shelley Chen <shchen@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/19553
Original-Reviewed-by: Furquan Shaikh <furquan@google.com>
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://chromium-review.googlesource.com/497404
