Set a temporary I2C base address during romstage.
TEST=Build and run on Galileo Gen2
Change-Id: I4b427c66a4e7e6d30cc611d4d3c40bb0ea36066d
Original-Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Original-Reviewed-on: https://review.coreboot.org/15006
Original-Reviewed-by: Martin Roth <martinroth@google.com>
(cherry-picked from commit 56c99f2850)
Signed-off-by: Martin Roth <martinroth@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/348421
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Select HSUART1 for console.
TEST=Build and run on Galileo Gen2
Change-Id: I4425af4dc8b3730b3fa2108d6cc2941bc22c2cdb
Original-Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Original-Reviewed-on: https://review.coreboot.org/15005
Original-Reviewed-by: Martin Roth <martinroth@google.com>
(cherry-picked from commit ca65bb7b4e)
Signed-off-by: Martin Roth <martinroth@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/348420
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Add link for TI TS5A23159 specification.
TEST=None
Change-Id: I2756ded963fc7597e4db1fa151bf62630b1108d9
Original-Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Original-Reviewed-on: https://review.coreboot.org/15003
Original-Reviewed-by: Martin Roth <martinroth@google.com>
(cherry-picked from commit 2a8cc3064e)
Signed-off-by: Martin Roth <martinroth@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/348419
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Only define BIT names if they are not already defined.
TEST=Build and run on Galileo Gen2
Change-Id: Ief4c4bb7a42a1bb2a7f46f13dc9b8bbb4d233e3c
Original-Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Original-Reviewed-on: https://review.coreboot.org/15002
Original-Reviewed-by: Martin Roth <martinroth@google.com>
(cherry-picked from commit d5493683ea)
Signed-off-by: Martin Roth <martinroth@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/348418
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Split out enabling FSP 1.1 support to prepare for enabling FSP 2.0
support.
TEST=Build and run on Galileo Gen2.
Change-Id: Ic4e814bcf61f9480f98e2d7bc7a1648dec43a07d
Original-Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Original-Reviewed-on: https://review.coreboot.org/15001
Original-Reviewed-by: Martin Roth <martinroth@google.com>
(cherry-picked from commit 5e808cb811)
Signed-off-by: Martin Roth <martinroth@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/348417
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Remove extra : following reigster type.
TEST=Build and run on Galileo Gen2
Change-Id: I57dd40a540d7b5371a6c45174f47a311b83a2aab
Original-Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Original-Reviewed-on: https://review.coreboot.org/14948
Original-Reviewed-by: Martin Roth <martinroth@google.com>
(cherry-picked from commit 6b24dfce74)
Signed-off-by: Martin Roth <martinroth@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/348416
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Migrate the clearing of the SMI interrupts and wake events from FSP into
coreboot.
TEST=Build and run on Galileo Gen2
Change-Id: Ia369801da87a16bc00fb2c05475831ebe8a315f8
Original-Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Original-Reviewed-on: https://review.coreboot.org/14945
Original-Reviewed-by: Martin Roth <martinroth@google.com>
(cherry-picked from commit 7f4b053980)
Signed-off-by: Martin Roth <martinroth@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/348415
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Rename the file pmc.c to lpc.c to prepare for further additions.
TEST=Build and run on Galileo Gen2
Change-Id: If98825d72878f0601f77bff8c766276dbda8a9ae
Original-Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Original-Reviewed-on: https://review.coreboot.org/14946
Original-Reviewed-by: Martin Roth <martinroth@google.com>
(cherry-picked from commit 773ee2bb17)
Signed-off-by: Martin Roth <martinroth@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/348414
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Migrate PCIe reset from PlatformPciHelperLib in QuarkFspPkg into
coreboot.
Change-Id: I1c33fa16b0323091e8f9bd503bbfdb8a253a76d4
Original-Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Original-Reviewed-on: https://review.coreboot.org/14944
Original-Reviewed-by: Martin Roth <martinroth@google.com>
(cherry-picked from commit 5ef051a53a)
Signed-off-by: Martin Roth <martinroth@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/348413
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Migrate google/ninja (AOpen Chromebox Commerical) from Chromium tree to
upstream, using google/rambi as a reference.
original source:
branch firmware-ninja-5216.383.B
commit 582a393 [Ninja, Sumo: Add SPD source for Hynix H5TC4G63CFR-PBA]
TEST=built and booted Linux on ninja with full functionality
blobs required for working image:
VGA BIOS (vgabios.bin)
firmware descriptor (ifd.bin)
Intel ME firmware (me.bin)
MRC (mrc.elf)
external reference code (refcode.elf)
Change-Id: I0f1892c24c08fa2d53185b2cf8b6f5a9001b2397
Original-Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Original-Reviewed-on: https://review.coreboot.org/14950
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
(cherry-picked from commit a87fcabd2e)
Signed-off-by: Martin Roth <martinroth@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/348412
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Modern platforms like Apollolake do not use XIP for early stages. In
such cases, cbfs_prog_stage_load should check for NO_XIP_EARLY_STAGES
instead of relying on ARCH_X86 to decide if a stage is XIP.
Change-Id: I1729ce82b5f678ce8c37256090fcf353cc22b1ec
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/15045
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/349015
Commit-Ready: Aaron Durbin <adurbin@chromium.org>
Tested-by: Aaron Durbin <adurbin@chromium.org>
The eSATA port of Lenovo T420 is port 3. I've checked it on an iGPU
model and a dGPU model.
Change-Id: I64bcc887140c1634dd1475d29e97780a5128d0be
Signed-off-by: Iru Cai <mytbk920423@gmail.com>
Reviewed-on: https://review.coreboot.org/14632
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Nicolas Reinecke <nr@das-labor.org>
Reviewed-on: https://chromium-review.googlesource.com/349013
Commit-Ready: Aaron Durbin <adurbin@chromium.org>
Tested-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
The Maxim Integrated 98357A codec is an I2S slave device that has no
control channel for configuration and instead provides a GPIO that is
used for channel selection and power down. This means it does not fit
into a bus hierarchy easily and is instead represented as a generic
device and found with a static bus scan using the devicetree.
This driver provides configuration options for passing the "sdmode" GPIO
descriptor as well as a second option for "sdmode delay" which can
configure the timing of the sdmode toggling in relation to the I2S
channel output.
In addition an GPIO can be provided to indicate to the driver whether
this device is present or not. This can be used for board designs that
may have different codec possibilities that are selected by HW strap.
Sample usage for this device driver:
device pci 1f.3 on
chip drivers/generic/max98357a
register "sdmode_gpio" = "ACPI_GPIO_OUTPUT(GPP_C6)"
register "sdmode_delay" = "100"
device generic 0 on end
end
end
Will result in the following code in the SSDT:
Scope (\_SB.PCI0.HDAS) {
Device (MAXM) {
Name (_HID, "MX98357A")
Name (_UID, Zero)
Name (_DDN, "Maxim Integrated 98357A Amplifier")
Method (_STA) { Return (0xF) }
Name (_CRS, ResourceTemplate () {
GpioIo (Exclusive, PullDefault, 0, 0, IoRestrictionOutputOnly,
"\\_SB.PCI0.GPIO", 0, ResourceConsumer)
})
Name (_DSD, Package () {
ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
Package () {
Package () { "maxim,sdmode-gpio", \_SB.PCI0.HDAS.MAXM, 0, 0, 0 }
Package () { "maxim,sdmode-delay", 100 }
Package () { "sdmode-delay", 100 }
}
})
}
}
Change-Id: Ia0bafe49bea9bbe4a3cc0f9f9cdb6f6390da57b5
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/15017
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/349065
Commit-Ready: Aaron Durbin <adurbin@chromium.org>
Tested-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
This adds a generic I2C driver that can be described in the devicetree
and used to generate ACPI objects in the SSDT based on the information
provided in the config registers.
The I2C bus can be configured and the device can provide an interrupt and
wake capability to the OS. A configuration option allows for a GPIO to
be provided that will be checked to determine if the device is preset on
the board before including it in the generated SSDT.
The driver is generic enough to be used for basic I2C devices that do
not have special configuration needs such as touchpads, touchscreens,
sensors, some audio codec/amplifiers, etc.
Sample usage for a touchpad device:
device pci 15.1 on
chip drivers/i2c/generic
register "hid" = ""ELAN0000""
register "desc" = "ELAN Touchpad"
register "irq" = "IRQ_EDGE_LOW(GPP_B3_IRQ)"
register "wake" = "GPE0_DW0_05"
device i2c 15.0 on end
end
end
Will result in the following code in the SSDT:
Scope (\_SB.PCI0.I2C1) {
Device (D015) {
Name (_HID, "ELAN0000")
Name (_UID, 0)
Name (_S0W, 4)
Name (_PRW, Package () { 5, 3 })
Method (_STA) { Return (0x0f) }
Name (_CRS, ResourceTemplate () {
I2cSerialBus (0x15, ControllerInitiated, 400000, AddressingMode7Bit,
"\\_S.PCI0.I2C1", 0, ResourceConsumer)
Interrupt (ResourceConsumer, Edge, ActiveLow) { 51 }
})
}
}
Change-Id: Ib32055720835b70e91ede5e4028ecd91894d70d5
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/15016
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/349064
Commit-Ready: Aaron Durbin <adurbin@chromium.org>
Tested-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Intel WiFi devices that support wake-on-wifi need to declare a Power
Resource for this wake pin. Typically this has been done with a
static declaration in the DSDT for each mainboard. By adding it to
the existing intel/wifi driver it can be done based on a
configuration register in the devicetree.
Additionally the WiFi regulatory domain can be set in the SSDT
directly instead of needing to use NVS to pass the value to the DSDT.
Also add device IDs for Wilkins Peak 2 and Stone Peak 2 devices that
are found on Chromebooks, and clean up a long line and some comment
formatting.
This was tested by booting on an HP Chromebook 13 device and comparing
that the output in the SSDT matches what used to be in the DSDT. The
WRDD value is read from VPD, if present, not from devicetree.cb.
Additionally the case where CONFIG_DRIVERS_INTEL_WIFI is enabled but
the wifi device is not described in devicetree.cb is tested to ensure
it still generates the AML but does not include the _PRW wake pin.
Example:
devicetree.cb:
device pci 1c.0 on
chip drivers/intel/wifi
register "wake" = "GPE0_DW0_16"
device pci 00.0 on end
end
end
VPD:
"region"="us"
SSDT.dsl:
Scope (\_SB.PCI0.RP01) {
Device (WIFI) {
Name (_UID, Zero)
Name (_DDN, "Intel WiFi")
Name (_ADR, 0x00000000)
Name (_PRW, Package () { 16, 3 })
Name (WRDD, Package () {
Zero,
Package () {
0x00000007,
0x00004150
}
})
}
}
Change-Id: I8b5c916f1a04742507dc1ecc9a20c19d3822b18c
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/15019
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/349063
Commit-Ready: Aaron Durbin <adurbin@chromium.org>
Tested-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Export the WRDD spec revision and WiFi domain type in the header
file so it can be used to generate ACPI tables by wifi drivers.
Change-Id: I3222eca723c52fe74a004aa7bac7167264249fd1
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/15018
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/349062
Commit-Ready: Aaron Durbin <adurbin@chromium.org>
Tested-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Add a universal hybrid graphics driver compatible with
all supported lenovo devices.
Hybrid graphics allows to connect the display panel to
either of one GPUs.
As there are only two GPUs one GPIO needs to be toggled.
In case the discrete GPU is activated the panel is routed to it.
On deactivation the panel is routed to the integrated
GPU.
On lenovo laptops the dGPU is always connected to PEG10 and it is
save to disable the PEG slot on dGPU deactivation.
Use common gpio.c for southbridge I82801IX.
Tested on Lenovo T520 using Nvidia NVS 5200m.
Removed Lenovo T430s from the list of supported devices,
as the T430s only supports "muxless Optimus".
Depends on change id:
Iccc6d254bafb927b6470704cec7c9dd7528e2c68
Ibb54c03fd83a529d1ceccfb2c33190e7d42224d8
I8bd981c4696c174152cf41caefa6c083650d283a
Iaf0c2f941f2625a5547f9cba79da1b173da6f295
I994114734fa931926c34ed04305cddfbeb429b62
Change-Id: I9b80b31a7749bdf893ed3b772a6505c9f29a56d1
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/12896
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@googlemail.com>
Reviewed-on: https://chromium-review.googlesource.com/349059
Commit-Ready: Aaron Durbin <adurbin@chromium.org>
Tested-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
The Nuvoton NAU8825 audio codec is an I2C device that has a number of
tunable parameters that can be provided to the kernel device driver for
basic configuration and optimal operation.
The configuration options are exposed to devicetree as registers and then
presented as Device Properties via ACPI to the operation system.
This sample configuration in devicetree:
device pci 19.2 on
chip drivers/i2c/nau8825
register "irq" = "IRQ_LEVEL_LOW(GPP_F10_IRQ)"
register "jkdet_enable" = "1"
register "sar_threshold_num" = "2"
register "sar_threshold[0]" = "0x0c"
register "sar_threshold[1]" = "0x1c"
device i2c 1a on end
end
end
Will generate the following code in the SSDT, trimmed for this commit
message as there are more properties that can be configured:
Scope (\_SB.PCI0.I2C4)
{
Name (_HID, "10508825")
Name (_UID, Zero)
Name (_DDN, "Nuvoton NAU8825 Codec")
Method (_STA) { Return (0xF) }
Name (_CRS, ResourceTemplate () {
I2cSerialBus (0x1A, ControllerInitiated, 0x61A80, AddressingMode7Bit,
"\_SB.PCI0.I2C4", 0, ResourceConsumer)
Interrupt (ResourceConsumer, Level, ActiveLow) { 0x3A }
})
Name (_DSD, Package () {
ToUUID ("daffd814-6eba-4d8c-8a91-bc9bff4aa301"),
Package () {
Package () { "nuvoton,jkdet-enable", 1 },
Package () { "nuvoton,sar-threshold-num", 2 },
Package () { "nuvoton,sar-threshold", Package () { 0x0c, 0x1c } }
}
})
}
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Change-Id: I480d72daf5ac3dded9b1cbb5fbc737b9dfde3834
Reviewed-on: https://review.coreboot.org/15015
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/349057
Commit-Ready: Aaron Durbin <adurbin@chromium.org>
Tested-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
ChromeEC is needed for EC controlled features to work properly.
This patch adds neccessary support in soc/intel so that mainboard
asl files can include the ChromeEC e.g. PNOT method and
LPCB and also the nvs fields.
BUG = 53096
TEST = This patch is needed by the mainboard specific ASL change to include
src/ec/google/chromeec/acpi/ec.asl
Change-Id: Icecc437df05cd3efb41579317a353fd22526e0c9
Signed-off-by: Shaunak Saha <shaunak.saha@intel.com>
Reviewed-on: https://review.coreboot.org/14967
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/349054
Commit-Ready: Aaron Durbin <adurbin@chromium.org>
Tested-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
On apollolake, the boot media layout is different in that the traditional
"BIOS" region contains another data structure with the boot assets such
as CSE firmware, PMC microcode, CPU microcode, and boot firmware to name
a few. This region is referred to as the IFWI. Add support for writing
the IFWI to a specified FMAP region to accommodate such platforms.
Change-Id: Ia61f12a77893c3dd3256a9bd4e0f5eca0065de26
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/14999
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/349053
Commit-Ready: Aaron Durbin <adurbin@chromium.org>
Tested-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Add ifwitool to list of tools to be built so that it can be used by the
build system.
Change-Id: Ifcfbfd87ad9b7ba3ea11cfbcf40894f3e0dae694
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/15013
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/349052
Commit-Ready: Aaron Durbin <adurbin@chromium.org>
Tested-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
All current Oak boards have PD chips with update speeds that range from
slow (Oak) to "OMG it's so awfully slow I could make a cup of coffee and
it would still not be done" (Elm). Set the flag that enables the "Your
system is applying a critical update. Please don't turn it off." message
on EC software sync so that our users don't accidentally carry it back
to the store and demand a refund while it's still not done booting.
BRANCH=None
BUG=chrome-os-partner:51145
TEST=Booted Oak in normal mode with a new EC-RW image. Confirmed that I
saw the magic screen.
Change-Id: I64ba698985d5fbcf2b94115df72b70a5319106ac
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/348787
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
The VBOOT_OPROM_MATTERS configuration option signals to vboot that the
board can skip display initialization in the normal boot path. It's name
is a left-over from a time when this could only happen by avoiding to
load the VGA option ROM on x86 devices, but nowadays we have other
boards that can skip their native display initialization paths too, and
the effect to vboot is the same. (Really, we should rename oprom_matters
and oprom_loaded to display_skippable and display_initialized or
something, but I don't think that's worth the amount of repositories
this would need to touch.)
The only effect this still has in today's vboot is to reboot and
explicitly request display initialization for EC software sync on
VBOOT_EC_SLOW_UPDATE devices (which we haven't had yet on ARM). Still,
the vboot flag just declares the capability (for skipping display init),
and it should be set correctly regardless of whether that actually makes
a difference on a given platform (right now). This patch updates all
boards/SoCs that have a conditional path based on
display_init_required() accordingly.
BRANCH=None
BUG=chrome-os-partner:51145
TEST=Booted Oak, confirmed that there's no notable boot time impact.
Change-Id: I75e5cdda2ba2d111ea50ed2c7cdf94322679f1cd
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/348786
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
This patch adds code to initialize the two DWC3 USB
host controllers, and uses them to initialize USB3.0
on the gru rk3399 board.
BRANCH=none
BUG=chrome-os-partner:52684
TEST=boot from USB3.0 on gru/kevin rk3399 platform
Change-Id: I796fa1133510876f75873d134ea752e1b52e40a8
Signed-off-by: Liangfeng Wu <wulf@rock-chips.com>
Signed-off-by: Douglas Anderson <dianders@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/347524
Commit-Ready: Brian Norris <briannorris@chromium.org>
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
1. Make the xHCI driver to support xHCI controller v1.1
2. And a new function xhci_ring_doorbell(), it aims to
add a memory barrier before ring the doorbell, ensure
all TRB changes are written to memory.
BRANCH=none
BUG=chrome-os-partner:52684
TEST=boot from USB on Kevin rk3399 platform
Change-Id: I4e38e04dc3c7d32ee4bb424a473c70956a3c3ea9
Signed-off-by: Liangfeng Wu <wulf@rock-chips.com>
Reviewed-on: https://chromium-review.googlesource.com/346831
Commit-Ready: Brian Norris <briannorris@chromium.org>
Tested-by: Douglas Anderson <dianders@chromium.org>
Reviewed-by: Douglas Anderson <dianders@chromium.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
From the User-Level ISA Specification v2.0:
"We do not mandate atomicity for misaligned accesses so simple
implementations can just use a machine trap and software handler to
handle misaligned accesses." ( http://riscv.org/specifications/)
Spike traps on unaligned accesses.
Change-Id: Ia57786916f4076cc08513f4e331c2deec9cfa785
Original-Signed-off-by: Jonathan Neuschfer <j.neuschaefer@gmx.net>
Original-Reviewed-on: https://review.coreboot.org/14983
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
(cherry-picked from commit 4acb0e7742)
Signed-off-by: Martin Roth <martinroth@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/348411
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
MMIO region of 256 KiB under 4 GiB is not decoded by SPI controller
by hardware design. Current code incorrectly specifies size of that
region to be 128 KiB. This change corrects the value to 256 KiB.
Change-Id: Idcc67eb3565b800d835e75c0b765dd49d1656938
Original-Signed-off-by: Andrey Petrov <andrey.petrov@intel.com>
Original-Reviewed-on: https://review.coreboot.org/14979
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
(cherry-picked from commit 204af8157d)
Signed-off-by: Martin Roth <martinroth@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/348409
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
This adds the website URL to the board info and also enables
the realtek nic reset function as per a previous patch.
Change-Id: I2cda120c59b55f0dd2ffa78d397b16beb13d6843
Original-Signed-off-by: Damien Zammit <damien@zamaudio.com>
Original-Reviewed-on: https://review.coreboot.org/14954
Original-Reviewed-by: Jonathan Neuschfer <j.neuschaefer@gmx.net>
Original-Reviewed-by: Martin Roth <martinroth@google.com>
(cherry-picked from commit b28a411362)
Signed-off-by: Martin Roth <martinroth@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/348408
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
One thing that is vital to this patch is the MAC address setting
in case the EEPROM/efuse is unconfigured.
Linux now recognises the default MAC address on GA-G41M-ES2L which
does rely on the default bios settings for the MAC address.
Change-Id: I32e070b545b4c6369686a7087b7ff838d00764e3
Original-Signed-off-by: Damien Zammit <damien@zamaudio.com>
Original-Reviewed-on: https://review.coreboot.org/14927
Original-Reviewed-by: Martin Roth <martinroth@google.com>
(cherry-picked from commit e983f0cb4b)
Signed-off-by: Martin Roth <martinroth@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/348407
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
This patch adds DMI/EP init to the board and fixes
a couple of minor things.
Change-Id: I10d0f6ce747b60499680e4dc229b7fcbb16cc039
Original-Signed-off-by: Damien Zammit <damien@zamaudio.com>
Original-Reviewed-on: https://review.coreboot.org/14926
Original-Reviewed-by: Martin Roth <martinroth@google.com>
(cherry-picked from commit 2abd3f9e1c)
Signed-off-by: Martin Roth <martinroth@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/348406
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
The values were obtained from vendor bios at runtime.
I am not 100% sure of the sequence required to initiate them,
but guessed from the gm45 code. There may be some status bytes
needed to be polled during the sequence that is missing,
but as I don't have bios writer's datasheet it's very hard
for me to know.
Change-Id: Idd205e0bab5f75e01c6e3a5dc320c08639f52db8
Original-Signed-off-by: Damien Zammit <damien@zamaudio.com>
Original-Reviewed-on: https://review.coreboot.org/14925
Original-Reviewed-by: Martin Roth <martinroth@google.com>
(cherry-picked from commit a090ae04c2)
Signed-off-by: Martin Roth <martinroth@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/348405
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Previously, due to a bug in devicetree and incorrect IRQ
settings in ACPI, SATA controller would not initialize
any HDDs in the OS, even though it worked in SeaBIOS.
The devicetree setting is not needed because SATA must
function in plain mode on this board, as combined mode
does not work at all.
Change-Id: I0036c4734de00b84cc3d64f38e4b1fd80fd1a25d
Original-Signed-off-by: Damien Zammit <damien@zamaudio.com>
Original-Reviewed-on: https://review.coreboot.org/14776
Original-Reviewed-by: Martin Roth <martinroth@google.com>
(cherry-picked from commit 2b2f465fcb)
Signed-off-by: Martin Roth <martinroth@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/348404
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Add a PCI driver for the skylake SD card device and have it generate
an entry in the SSDT for the card detect GPIO if it is provided by the
mainboard in devicetree.
This sets up a card detect GPIO configuration that will trigger an
interrupt on both edges with a 100ms debounce timeout and can wake the
SD controller from D3 state.
The GpioInt() entry is bound to the cd-gpio device property which will
be consumed by the kernel driver.
The resulting ACPI output in the SSDT will be combined with the SDXC
device declaration in the DSDT.
Example:
Scope (\_SB.PCI0.SDXC)
{
Name (_CRS, ResourceTemplate () {
GpioInt (Edge, ActiveBoth, SharedAndWake, PullNone, 10000,
\_SB.PCI0.GPIO, 0, ResourceConsumer) { 35 }
})
Name (_DSD, Package () {
ToUUID (daffd814-6eba-4d8c-8a91-bc9bbf4aa301),
Package () {
Package () { cd-gpio, Package () { \_SB.PCI0.SDXC, 0, 0, 1 } }
}
})
}
Change-Id: Ie4c1bfadd962cf55a987edb9ef86e92174205770
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/14995
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
(cherry-picked from commit b25a45ca46)
Signed-off-by: Martin Roth <martinroth@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/348403
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Minor cleanups in pci_devs.h for indentation and newlines to be
consistent throughout the file.
Change-Id: I522df141a6b33d918cfb3de1b9019c0c4a73e3e5
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/14994
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
(cherry-picked from commit 98d69c0627)
Signed-off-by: Martin Roth <martinroth@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/348402
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Add the Audio DSP device for skylake as a PCI driver with a static
scan_bus handler so generic devices can be declared under it.
This is for devices like the Maxim 98357A which is connected on the
I2S bus for data but has no control channel bus and instead just has
a GPIO for channel selection and power down control and needs to
describe that GPIO connection to the OS via ACPI.
Change-Id: Iae02132ff9c510562483108ab280323f78873afd
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/14993
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
(cherry-picked from commit 026003e621)
Signed-off-by: Martin Roth <martinroth@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/348401
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Add the I2C devices to skylake with the scan_bus handler for SMBUS
devices so that I2C-based devices can be declared in devicetree.cb
and get initialized properly during ramstage.
This does not yet provide the I2C driver, but it allows for devices
that are declared in devicetree.cb to provide ACPI tables to the OS.
Change-Id: I9dfe4a06a8b0bc549a2b0e2d7c033c895188ba30
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/14992
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
(cherry-picked from commit 0d8bb7427b)
Signed-off-by: Martin Roth <martinroth@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/348400
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
