Including the terminating null, 17 characters were being written to the
field, overwriting the a byte of the size field.
Fortunately, the size was updated soon after this.
Fixes coverity warning 1229570 - Destination buffer too small.
BUG=None
BRANCH=None
TEST=None
Change-Id: Iaf9e8ed36d1a689bff4a40593e2bb075d3298353
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/15889
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://chromium-review.googlesource.com/365314
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
A few things are currently missing:
- The trap handler doesn't set the stack pointer, which can easily
result in trap loops or memory corruptions.
- The SBI trampolin page (as described in version 1.9 of the RISC-V
Privileged Architecture Specification), has been removed for now.
BUG=None
BRANCH=None
TEST=None
Change-Id: I7c86da1322e5683de4410fa50300243e29f029b2
Signed-off-by: Jonathan Neuschfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/15591
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-on: https://chromium-review.googlesource.com/365313
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
And do the detection just before the initialization.
BUG=None
BRANCH=None
TEST=None
Change-Id: I60b2aed845d1a75516b14a7721050565e5535f73
Signed-off-by: Jonathan Neuschfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/15831
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-on: https://chromium-review.googlesource.com/365312
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This patch adds apollolake soc specific change. DPTF
ASL files are now in src/soc/intel/common so that
they can be reused but different soc can have different values
e.g., for skylake cpu soc thermal reporting device is at
Bus 0, Device 4, Function 0 while for apollolake it is Bus 0, Device 0,
Function 1. This patch adds a dptf asl file in soc directory where we
can define all values which can change across soc's and can be
included in mainboard dptf asl.
BUG=chrome-os-partner:53096
BRANCH=None
TEST=In Amenia and Reef board verify that the thermal zones are
enumerated under /sys/class/thermal in Amenia and Reef board.
Navigate to /sys/class/thermal, and verify that a thermal
zone of type TCPU exists there.
Change-Id: I250bafc6f6113eb74319d64abc7f1d1649baee31
Signed-off-by: Shaunak Saha <shaunak.saha@intel.com>
Reviewed-on: https://review.coreboot.org/15619
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/365227
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Squash of two commits:
List of activity performing in this patch
- early PCH programming
- early SA programming
- early CPU programming
- mainborad early gpio programming for UART and SPI
- car setup
- move chipset programming from verstage to post console
BUG=chrome-os-partner:55357
BRANCH=none
TEST=Built and booted kunimitsu till POST code 0x34
intel/skylake: Fix UART build options
1. skylake does not support UART over I/O. So, NO_UART_ON_SUPERIO needs
to be selected by default.
2. Move BOOTBLOCK_CONSOLE under UART_DEBUG.
3. Include bootblock/uart.c only if UART_DEBUG is selected.
Change-Id: Ie0b473294943aa087997a95c81601ed9584f8cb9
Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com>
Signed-off-by: Naveen Krishna Chatradhi <naveenkrishna.ch@intel.com>
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/15785
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/16025
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
Reviewed-on: https://chromium-review.googlesource.com/365226
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
EVT1 has two board IDs.
Use binary first mode of base3 encoding for board ID.
BUG=chrome-os-partner:55320
TEST=None.
BRANCH=None
Change-Id: I6e95c7be4a6d28a0aae38b0838bd2ab71d288ba1
Signed-off-by: Kan Yan <kyan@google.com>
Reviewed-on: https://chromium-review.googlesource.com/364623
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Reviewed-by: Suresh Rajashekara <sureshraj@chromium.org>
Coming Kevin revisions will switch back to an I2C TPM. This patch adds
the required configuration options and code to support that. Since the
TPM type can currently only be changed at compile time, we can no longer
support older Kevins with the same image. In order to build for Kevin
revisions < 5, you have to explicitly override the CONFIG_GRU_HAS_TPM2.
BRANCH=None
BUG=chrome-os-partner:55523
TEST=Compiled both Kevin and Gru, confirmed that bootblock and verstage
binary had the appropriate code differences.
Change-Id: I81a15c9fb037a7ca2d69818e46cbb4f9a5ae1989
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/364222
Reviewed-by: Douglas Anderson <dianders@chromium.org>
This patch adds support for the Gru rev1 board. This board differs from
rev0 by no longer relying on the I2C backlight booster and requiring the
same ODT SDRAM settings as newer Kevin boards.
BRANCH=None
BUG=chrome-os-partner:55087
TEST=None
Change-Id: I3cb49bc644190f35300e6c618b2934956fa88e5b
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/364624
Reviewed-by: Douglas Anderson <dianders@chromium.org>
1. Currenty, boot reason is being added to elog only for some
ARM32/ARM64 platforms. Change this so that boot reason is logged by
default in elog for all devices which have CHROMEOS selected.
2. Add a new option to select ELOG_WATCHDOG_RESET for the devices that
want to add details about watchdog reset in elog. This requires a
special region WATCHDOG to be present in the memlayout.
3. Remove calls to elog add boot reason and watchdog reset from
mainboards.
BUG=chrome-os-partner:55639
BRANCH=None
TEST=None
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/15897
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
Change-Id: I91ff5b158cfd2a0749e7fefc498d8659f7e6aa91
Reviewed-on: https://chromium-review.googlesource.com/364021
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
If the system is in recovery, store the newly generated MRC data using a
dummy version which is not legit. This ensures that on next normal boot,
new MRC data will be generated and stored.
BUG=chrome-os-partner:55699
BRANCH=None
TEST=None
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/15828
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Change-Id: Ib13e8c978dc1b4fc8817fab16d0e606f210f2586
Reviewed-on: https://chromium-review.googlesource.com/364013
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Currently, coreboot performs an erase of the entire MRC cache region on
flash if there is a version mismatch for the MRC data. Instead of doing
that, store the new MRC data in the next available slot, if there is
enough space available in the cache region.
BUG=chrome-os-partner:55699
BRANCH=None
TEST=None
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/15915
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Change-Id: Ib24a94f0a47c79941ed9f60095360ae3aad5540b
Reviewed-on: https://chromium-review.googlesource.com/364012
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
The slippy board was a proof of concept device that has never
made it out in the wild. Moreover, I don't think any of these
boards exist any longer.
BUG=None
BRANCH=None
TEST=None
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/15902
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
Change-Id: I24fb08d9be35b2367e7aa64520ce5778ab861535
Reviewed-on: https://chromium-review.googlesource.com/364011
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
The bolt board was a proof of concept device that has never
made it out in the wild. Moreover, I don't think any of these
boards exist any longer.
BUG=None
BRANCH=None
TEST=None
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/15901
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
Change-Id: I5ca055d448659a2b8e2eafcfc2114a6b8f8a56a4
Reviewed-on: https://chromium-review.googlesource.com/364010
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
The monitor/mwait is broken on Apollolake. So use ACPI legacy
mwait IO redirection as a work around
BUG=chrome-os-partner:55110
BRANCH=None
TEST=None
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-on: https://review.coreboot.org/15890
Tested-by: build bot (Jenkins)
Reviewed-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Change-Id: I2e1834130d9586b4310466d3549d19bf427ffe24
Reviewed-on: https://chromium-review.googlesource.com/363939
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
This renames the VB_SOURCE variable to VBOOT_SOURCE in the build system,
providing increased clarity about what it represents.
Since the submodule itself is called "vboot", it makes sense to use that
name in full instead of a very shortened (and confusing) version of it.
BUG=None
BRANCH=None
TEST=None
Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
Reviewed-on: https://review.coreboot.org/15824
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Change-Id: Ib343b6642363665ec1205134832498a59b7c4a26
Reviewed-on: https://chromium-review.googlesource.com/363938
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
This introduces a CHROMEEC_SOURCE variable used for indicating the CrOS
EC source path, with a fallback to 3rdparty/chromeec.
This allows specifying an external path for the CrOS EC source path.
BUG=None
BRANCH=None
TEST=None
Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
Reviewed-on: https://review.coreboot.org/15765
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Change-Id: I9792c7f21597127a385b961b65a00d44cfa37146
Reviewed-on: https://chromium-review.googlesource.com/363937
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Quark does not support the rdmsr and wrmsr instructions. Use SOC
specific routines to configure the MTRRs on Quark based platforms.
Add cpu_common.c as a build dependency to provide access to the routine
cpu_phys_address_size.
TEST=Build and run on Galileo Gen2
BUG=None
BRANCH=None
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/15846
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Change-Id: I43b7067c66c5c55b42097937e862078adf17fb19
Reviewed-on: https://chromium-review.googlesource.com/363936
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Quark does not support the rdmsr and wrmsr instructions. In this case
use a SOC specific routine to support the setting of the MTRRs. Migrate
the code from FSP 1.1 to be x86 CPU common.
Since all rdmsr/wrmsr accesses are being converted, fix the build
failure for quark in lib/reg_script.c. Move the soc_msr_x routines and
their depencies from romstage/mtrr.c to reg_access.c.
TEST=Build and run on Galileo Gen2
BUG=None
BRANCH=None
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/15839
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Change-Id: Ibc68e696d8066fbe2322f446d8c983d3f86052ea
Reviewed-on: https://chromium-review.googlesource.com/363935
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Now hardcode maximum memory frequency capability to 800MHz, as
all chipsets in x4x family support PC2-6400 according to the datasheet.
CAS latency detection also relies on this, and has been cleaned up.
Ram initialization does not work with FSB 1333MHz / DDR2 800MHz combination,
so disable this combination for now, and reduce to 667MHz instead.
Still don't know why this is the case, but FSB1333/667 works.
These changes should now allow existing configurations to continue working,
while providing support for previously unworking configurations, due to
previous buggy CAS latency detection code.
TESTED: on GA-G41M-ES2L
CPU: E5200 @ 2.50GHz (FSB 800MHz)
2x 1GB 667MHz hynix worked @ 667
1x 2GB 800Mhz ARAM worked @ 800
1x 1GB 667Mhz StarRam worked @ 667
2x 2GB 800Mhz (generic) worked @ 800
BUG=None
BRANCH=None
TEST=None
Signed-off-by: Damien Zammit <damien@zamaudio.com>
Reviewed-on: https://review.coreboot.org/15818
Tested-by: build bot (Jenkins)
Reviewed-by: Kysti Mlkki <kyosti.malkki@gmail.com>
Change-Id: I1ddd7827ee6fe3d4162ba0546f738a8f9decdf93
Reviewed-on: https://chromium-review.googlesource.com/363934
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Allow bootblock to get access to the static device tree like
other early stages. device_romstage.c was renamed to
device_simple.c to better articulate the usage since it's not
just being used in romstage.
BUG=chrome-os-partner:55357
BRANCH=None
TEST=None
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/15837
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Tested-by: build bot (Jenkins)
Change-Id: I3d63d2754c737cc738c09a3e3b3b468362fb78d1
Reviewed-on: https://chromium-review.googlesource.com/363933
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
All mainboards (nyans) utilizing the cache_policy option
has it set to DCACHE_WRITETHROUGH. This option is for setting
the framebuffer's cache attribute. However, this option is
reliant on an architecture-specific enumeration. Just remove
the option and use DCACHE_WRITETHROUGH across the board. If
someone wants to reconfigure it at a later date one can
introduce a non-architecture specific option.
BUG=None
BRANCH=None
TEST=None
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/15838
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Change-Id: I6a0848231f5e28d36ec2d56b239bed67619fe5a7
Reviewed-on: https://chromium-review.googlesource.com/363932
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Place a map file for the postcar stage and place it into
build/cbfs/fallback.
TEST=Build and run on Galileo Gen2
Change-Id: I349c06e3c610db5b3f2511083208db27110c34d0
Original-Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Original-Reviewed-on: https://review.coreboot.org/15845
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/363390
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Move the ramstage files to the beginning of the section. Eliminate
duplicate conditionals.
TEST=Build and run on Galileo Gen2
Change-Id: I461a5b78a76bd0d2643b85973fd0a70bc5e89581
Original-Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Original-Reviewed-on: https://review.coreboot.org/15892
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/363389
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Move the postcar commands to in between romstage and ramstage. Add the
stage header.
TEST=Build and run on Galileo Gen2
Change-Id: I530da6afd8ccbcea217995ddd27066df6d45de22
Original-Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Original-Reviewed-on: https://review.coreboot.org/15844
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/363387
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
The removal of ELOG_FLASH_BASE and ELOG_FLASH_SIZE resulted
in the FMAP region for the eventlog to be honored. However,
certain systems seem to have a large eventlog region that
wasn't being used in practice. Because of the malloc() in the
eventlog init sequence a large allocation was now being requested
that can exhaust the heap. Put back the 4KiB capacity until
the resource usage is fixed.
BUG=chrome-os-partner:55593
Change-Id: Ib54b396b48e5be80f737fc3feb0d58348c0d2844
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/15835
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Reviewed-by: Furquan Shaikh <furquan@google.com>
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/363386
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
XIP cachelines contain the executable to run, we never want
that to get modified. With the change such erronous writes
are ignored and next cacheline miss will fetch from boot
media (SPI / FWH flash).
Change-Id: I52b62866b5658e103281ffa1a91e1c64262f3175
Original-Signed-off-by: Kysti Mlkki <kyosti.malkki@gmail.com>
Original-Reviewed-on: https://review.coreboot.org/15778
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/363385
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Match the definition and use of these variable with haswell, such that
DCACHE_RAM_MRC_VAR_SIZE is not included in DCACHE_RAM_SIZE.
Change-Id: I5af20f63cd0cb631d39f7c7fe0e2a99ebd3ce986
Original-Signed-off-by: Kysti Mlkki <kyosti.malkki@gmail.com>
Original-Reviewed-on: https://review.coreboot.org/15761
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/363384
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
The build fails during postcar when ULZMA compression is not selected.
Fix cbfs.c to support LZ compression for ramstage as well.
The build error is:
build/postcar/lib/cbfs.o: In function `cbfs_load_and_decompress':
/home/lee/coreboot/public/src/lib/cbfs.c:116: undefined reference to
`ulzman'
make: *** [build/cbfs/fallback/postcar.debug] Error 1
TEST=Build and run on Galileo Gen2
Change-Id: I7fa8ff33c0d32e0c5ff5de7918e13e6efb1df38e
Original-Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Original-Reviewed-on: https://review.coreboot.org/15841
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/363383
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Separate NO_XIP_EARLY_STAGES from loading FSP-M into cache-as-RAM.
Quark executes romstage directly from the SPI flash part (in-place),
but loads FSP-M into ESRAM. This split occurs because ESRAM is too
small to hold everything while debugging.
Platforms executing FSP-M directly from the SPI flash need to select
FSP_M_XIP.
TEST=Build and run on Galileo Gen2.
Change-Id: Ib5313ae96dcec101510e82438b1889d315569696
Original-Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Original-Reviewed-on: https://review.coreboot.org/15848
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/363382
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
