Add "(LB) " to all log messages to differentiate them visually
from the rest of the boot messages. This is similar to what
Xen does when booting (it prefixes all log messages with "(XEN) ").
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://coreboot.org/repository/LinuxBIOSv3@209 f3766cd6-281f-0410-b1cd-43a5c92072e9
Comitting IP checksum code, and its usage in linuxbios table creation.
Mods to the dts, so that the device ops for the domain are set to the
proper structure. This change is important. It gets rid of the obscure,
confusing use of the enable_dev function to pick the right ops for a
device. It makes the ops initilization very clear at the top level, in
the dts. This has been tested and works, linux boots on Bochs under
this version.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://coreboot.org/repository/LinuxBIOSv3@191 f3766cd6-281f-0410-b1cd-43a5c92072e9
- EXPERIMENTAL - enable experimental/incomplete code/boards
- EXPERT - enable expert/developer options
- LOCALVERSION - set a string to append to the LinuxBIOS version
Mark BOARD_EMULATION_QEMU_POWERPC and CONSOLE_USB as experimental for now.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://coreboot.org/repository/LinuxBIOSv3@184 f3766cd6-281f-0410-b1cd-43a5c92072e9
add debug printks.
make dtc put 'root' as the first_node, instead of making the last node
be the first node .... much happier in linuxbios.
sprintf is broken ... dammit. I hope someone will fix it. I've got about
another week of full-time I can spend on this and then I go back to part
time. So I'm going to need some help soon.
other fixups, and also, make the dts conform to the needs of the device
tree. So we have a domain0 and a device (0,0) that is the north.
Mostly things are working, but we're STILL not getting any memory in the
LB tables from the north. The device tree is a bitch.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://coreboot.org/repository/LinuxBIOSv3@175 f3766cd6-281f-0410-b1cd-43a5c92072e9
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://coreboot.org/repository/LinuxBIOSv3@172 f3766cd6-281f-0410-b1cd-43a5c92072e9
Phase 1: done
Phase 2: early setup ...
Phase 2: done
Phase 3: Enumerating buses...
qemu-x86 enable_dev done
dev_phase3_scan: scanning Root Device
scan_static_bus for root(Root Device)
cpus: Unknown device path type: 0
cpus() enabled
i440bxemulation_enable_dev:
i440bxemulation_enable_dev: DONE
northbridge_intel_i440bxemulation() enabled
northbridge_intel_i440bxemulation() scanning...
dev_phase3_scan: scanning
pci_scan_bus start
PCI: pci_scan_bus for bus 00
PCI: scan devfn 0x0 to 0xff
PCI: devfn 0x0
PCI: pci_scan_bus pci_scan_get_dev returns dev <NULL>
Change dts compiler to emit a new struct member, dtsname, for devices,
so we can get actual useful names for things.
Several mods and printks added.
printk(BIOS_SPEW
gives no output for reasons I don't understand.
Next in line is bringing back v2 support for pci, but not doing it the
way v2 does it.
note the cpus() printk above. cpus don't have a valid path yet.
We still need to work out the dts syntax for systems with multiple links
(opteron)
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://coreboot.org/repository/LinuxBIOSv3@163 f3766cd6-281f-0410-b1cd-43a5c92072e9
Some minor cosmetic fixes (trivial).
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://coreboot.org/repository/LinuxBIOSv3@155 f3766cd6-281f-0410-b1cd-43a5c92072e9
Plus some small trivial reformatting of comments in stage0_i586.S
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://coreboot.org/repository/LinuxBIOSv3@146 f3766cd6-281f-0410-b1cd-43a5c92072e9
renamed the phase3 etc. to stuff like phase3_scan, so you can get a
rought idea what it is. The names mean more.
adding pci_device and, at the same time, showing how we can get rid of
the really ugly stuff that crept in. note you can specify ops in the
dts, which avoids the need for hideous stuff like this:
static void enable_dev(struct device *dev)
{
/* Set the operations if it is a special bus type */
if (dev->path.type == DEVICE_PATH_PCI_DOMAIN) {
dev->ops = &pci_domain_ops;
pci_set_method(dev);
}
else if (dev->path.type == DEVICE_PATH_APIC_CLUSTER) {
dev->ops = &cpu_bus_ops;
}
}
So that foolishness is gone.
added delay functions.
Note that we have include/lib.h, and define all the functions in there,
instead of in lots of fiddly includes.
Brought back the enable op, once I understood it; renamed it to
something that makes sense.
I'll be on a plane soon, will continue to work, but at least you can see
what's going on here.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://coreboot.org/repository/LinuxBIOSv3@139 f3766cd6-281f-0410-b1cd-43a5c92072e9
because not all emulators get the ram size registers right, or so we
hear.
This northbridge is still incomplete. We are not just copying the v2
one, as we are trying to undo the various hacks that crept in over the
years, due to limitations in the v2 device model. Just look at the
i440bx in v2 and you can see what I mean. We are working to find a
better way to get the job done than those hacks. They are just too
confusing for people to follow.
add an include for the northbridge makefile into the qemu Makefile.
Re-order the includes in arch/x86/Makefile so we can pick up .o files
from other places. Add a STAGE2_CHIPSET_OBJ for objects defined in those
makefiles included in mainboard.
Current issues: the enable_dev function for the i440bx is not getting
called. Enable_dev should be renamed to phase3_setup or something that
actually means something. The name as it is is totally useless.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://coreboot.org/repository/LinuxBIOSv3@138 f3766cd6-281f-0410-b1cd-43a5c92072e9
resource .c functions -- sigh -- this will be next.
fix types, fix some usage, but we do not yet generate pirqi, mptables,
or acpi. This will be next.
This code will be called from phase6 in stage 2, and probably
attached to a cpu. Or, it will be inline in the stage2.c code, since
the need for tables is generic.
I'm also going to move the cryptic usage of lgdt from here to stage 2,
phase 2, of the cpu code. The device model improvements are making it
easier to think about when things happen, we are finding.
I'm going to get lunch and go see some of brussels. It's a miserable day
but ...
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://coreboot.org/repository/LinuxBIOSv3@130 f3766cd6-281f-0410-b1cd-43a5c92072e9
warnings for developing/debugging, but not for the default LinuxBIOS build.
These are purely cosmetic changes, no build process changes (trivial).
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://coreboot.org/repository/LinuxBIOSv3@126 f3766cd6-281f-0410-b1cd-43a5c92072e9
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/LinuxBIOSv3@107 f3766cd6-281f-0410-b1cd-43a5c92072e9
* remove some warnings
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/LinuxBIOSv3@95 f3766cd6-281f-0410-b1cd-43a5c92072e9
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/LinuxBIOSv3@94 f3766cd6-281f-0410-b1cd-43a5c92072e9
Fix up dts to set up ops struct member. Fix dts for qemu mainboard.
We are getting past stage2 now, it is time for elfboot.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://coreboot.org/repository/LinuxBIOSv3@88 f3766cd6-281f-0410-b1cd-43a5c92072e9
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/LinuxBIOSv3@86 f3766cd6-281f-0410-b1cd-43a5c92072e9
should -- KISS should apply. So, the first function called via LAR is the first
function in the file.
For now, reorder this so main is first.
We now are getting into stage 2.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://coreboot.org/repository/LinuxBIOSv3@82 f3766cd6-281f-0410-b1cd-43a5c92072e9
This builds but dependencies need work; it takes a few
make -k
passes :-)
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://coreboot.org/repository/LinuxBIOSv3@80 f3766cd6-281f-0410-b1cd-43a5c92072e9
It's slightly broken by the merge, but we want to get it in.
Will be fixed tomorrow.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://coreboot.org/repository/LinuxBIOSv3@79 f3766cd6-281f-0410-b1cd-43a5c92072e9
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/LinuxBIOSv3@71 f3766cd6-281f-0410-b1cd-43a5c92072e9
Use standard LinuxBIOS license header (trivial, no semantic changes).
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://coreboot.org/repository/LinuxBIOSv3@63 f3766cd6-281f-0410-b1cd-43a5c92072e9
accordance to the newboot document:
* reset vector (16 bytes)
* vpd (240bytes)
* boot block (8k - 256b)
* lar archive (256-8 k)
The boot block is kind of simple, still. It enables pmode, car, and
starts looking for an initram module in the lar archive.
Note: This doesnt do much at the moment,
as gas seems to produce buggy code in init.S.
Take this as a suggestion of how it might work and please provide
patches fixing it and bringing it into shape.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/LinuxBIOSv3@62 f3766cd6-281f-0410-b1cd-43a5c92072e9
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://coreboot.org/repository/LinuxBIOSv3@61 f3766cd6-281f-0410-b1cd-43a5c92072e9
* add config.h so the Ron's latest changes build.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/LinuxBIOSv3@60 f3766cd6-281f-0410-b1cd-43a5c92072e9
expect to hear about this change. Note that Stefan and I have discussed
this change and feel it is at least worth trying.
Also, please be aware that this change is backed by a
lot of experience with LinuxBIOS users and usage of the last 7 years.
First I detail changes, then I detail why.
Major changes for the new config system.
Selection of object files, and variable setting, is now controlled by
Kconfig.
There is only one dts now. It is in the mainboard file. It may later
move to the target file -- we will see.
The dts is in two parts, seperated by %%. The first part is a
fairly standard dts, and the dtc will automatically generate a device
tree from it. The device tree is composed of generic structures. These
structures are identical to those of the old V2 device tree. All the
hierarchy and parent/child/sibling relationships appear to be correctly
generated. This means that all the v2 code will work without change.
For each node in the tree, if the node has a property named 'config',
then the dtc will generate a reference to a structure and an include
directive for a path -- much as in the old Config tool.
Example: here is a fragment of a dts
==========
north {
config = "northbridge,intel,i440bx";
};
%%
struct northbridge_intel_i440bx_config north = {
.whatever = 1;
};
===========
The dtc will create:
#include <northbridge/intel/i440gx/config.h>
struct northbridge_intel_i440bx_config north = {
.whatever = 1;
};
struct device dev_north {
.chip_ops = &northbridge_intel_i440bx_ops;
.chip_info = &north;
.
.
.
};
So the programmer specifies the tree structure in dts form, indicates
which devices have a config entry, and sets up the C code for the
config. I have worked with this and am finding it very easy to use. I
think this is the way to go. Plus, we are getting rid of most of the
include hell of the old Config system.
Note that the config node is OPTTONAL! If you do not set it then no
structure usage/include will occur.
WHY?
Here is my setup for v3. I think this is good. I like it and am
finding it easy to work with.
Basically, the old config system combined makefile generation, tree
generation, and chip struct initialization in one file -- config.lb.
What we need are four things:
1. selection of .c files to build the bios with
2. the device tree -- this is built with generic structures defined in
include/device/device.h
3. The per-chip structures, usually defined in, e.g.,
northbridge/intel/i440bx/chip.h
4. setting of variables such as baud rate, etc.
Again, this was all done in Config.lb, spread all over the place, like this:
config chip.h
object superio.o
This was hard for people. So we moved the makefile stuff out into the
Kconfig system. This change eliminates (1) and (4) above.
OK, what's left? Well, with our plans from last October, we had device
object model tree stuff, AND still had chip struct initialization in
one file. (2) and (3) above. This is tough, because I was fighting the
mapping of DTS stuff to the C code. It was getting just as ugly as the
old Config.lb. I have been struggling with this for months and it just
wasn't going anywhere.
But it's way too hard to set up the device tree by hand -- I've tried
it. OTOH, it's really easy to set up the per-chip stuff by hand --
I've tried that too. I did a search via:
find ~/src/LinuxBIOSv2/src/ -name chip.h -print
and looked at them all. These files are really simple. There's no
reason to get too tricky, as there is nothing worth getting tricky
about. The problem is the device tree, not these simple chip info
structs.
So, here's the solution.
The ONLY dts is in the mainboard directory. There is no equivalent of
Config.lb in the south, north, cpu, all that stuff any more. The
Kconfig and Makefile in those directories replaced the build-related
functions of Config.lb.-- (1) and (4) above. The only thing left was
chip.h anyway (3) above.
But how can we express the settings in chip.h via the DTS? IT's been
very hard to get this going.
So, here is the trick. The dts in the mainboard directory divides into
two parts. The first part is the standard dts. The second part is the
C code. They are seperated, as in lex and yacc, with a %%.
Here is the dts for qemu (note that the cpus keyword is still not
right, and maybe this structure needs to change; i'm not that worried
about that too much, just the big picture I'm discussing here). Also,
note I'm working with some new properties, e.g. pcipath and pcidomain
-- if these properties exist ina node, then I create initialized
structure members for them. Also see enabled and on_mainboard --
properties, but I catch them and use them.
/{
cpus {
config="mainboard,emulation,qemu-i386";
emulation,qemu-i386@0{
enabled;
on_mainboard;
device_type = "cpu";
name = "emulation,qemu-i386";
pcidomain = "0";
/* the I/O stuff */
northbridge,intel,440bx{
pcipath = "0,0";
southbridge,intel,piix4{
};
};
};
};
};
%%
/* the user sets up these structs */
struct mainboard_emulation_qemu_i386_config cpus = {
.nothing = 1,
};
You can see the device tree stuff at top. If a given node has a
property named 'config', then that means what the old 'chip' thing
meant in Config.lb. The dtc will generate an #include to pull in a
file with the path name specified in the config property. The dtc will
not set up the per-chip struct, but it will set up a pointer to a
struct when it sets up the device tree. Note that at bottom, it's up
to you to set up the initialized struct. But this was always the easy
part anyway. Instead of wacky pseudo-C like we had in config.lb, we
just do real C. It's easy. Here is what the dtc generates.
#include <device/device.h>
#include <device/pci.h>
#include <mainboard/emulation/qemu-i386/config.h>
struct device dev_southbridge_intel_piix4;
struct device dev_northbridge_intel_440bx;
struct device dev_emulation_qemu_i386_0;
struct device dev_cpus;
struct device dev_root;
extern struct chip_operations mainboard_emulation_qemu_i386_ops;
struct mainboard_emulation_qemu_i386_config cpus = {
.nothing = 1,
};
struct device dev_root = {
.path = { .type = DEVICE_PATH_ROOT },
.links = 1,
.link = {
[0] = {
.dev = &dev_root,
.link = 0,
.children = &dev_cpus
},
},
.bus = &dev_root.link[0],
};
struct device dev_cpus = {
.chip_ops = &mainboard_emulation_qemu_i386_ops,
.chip_info = &cpus,
.links = 1,
.link = {
[0] = {
.dev = &dev_cpus,
.link = 0,
.children = &dev_emulation_qemu_i386_0
},
},
.bus = &dev_root.link[0],
.next = &dev_root,
};
struct device dev_emulation_qemu_i386_0 = {
.enabled = 1,
.on_mainboard = 1,
.path = {.type=DEVICE_PATH_PCI_DOMAIN,.u={.pci_domain={ .domain = 0 }}}
,
.links = 1,
.link = {
[0] = {
.dev = &dev_emulation_qemu_i386_0,
.link = 0,
.children = &dev_northbridge_intel_440bx
},
},
.bus = &dev_cpus.link[0],
.next = &dev_cpus,
};
struct device dev_northbridge_intel_440bx = {
.path = {.type=DEVICE_PATH_PCI,.u={.pci={ .devfn = PCI_DEVFN(0,0)}}},
.links = 1,
.link = {
[0] = {
.dev = &dev_northbridge_intel_440bx,
.link = 0,
.children = &dev_southbridge_intel_piix4
},
},
.bus = &dev_emulation_qemu_i386_0.link[0],
.next = &dev_emulation_qemu_i386_0,
};
struct device dev_southbridge_intel_piix4 = {
.bus = &dev_northbridge_intel_440bx.link[0],
.next = &dev_northbridge_intel_440bx,
};
This compiles just fine.
I think this is the right way to go, comments to me.
But, note, IT COMPILES. And it's simple. And, it will work with our
current device tree code!
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://coreboot.org/repository/LinuxBIOSv3@59 f3766cd6-281f-0410-b1cd-43a5c92072e9
* fix arch/io.h to use consistent types
* add compression code and start integration into Kconfig
* update to newer version of Kconfig, and rename some occurences
of "Linux" to "LinuxBIOS"
* set up Make framework to create linuxbios.rom
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Ronald G Minnich <rminnich@lanl.gov>
git-svn-id: svn://coreboot.org/repository/LinuxBIOSv3@55 f3766cd6-281f-0410-b1cd-43a5c92072e9
header in some other files.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://coreboot.org/repository/LinuxBIOSv3@54 f3766cd6-281f-0410-b1cd-43a5c92072e9
These are all trivial changes.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://coreboot.org/repository/LinuxBIOSv3@50 f3766cd6-281f-0410-b1cd-43a5c92072e9
Signed-off-by: Segher Boessenkool <segher@kernel.crashing.org>
Acked-by: Peter Stuge <peter@stuge.se>
Acked-by: Ronald G Minnich <rminnich@gmail.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://coreboot.org/repository/LinuxBIOSv3@47 f3766cd6-281f-0410-b1cd-43a5c92072e9
