a reasonable timeout of 50usecs (timeout value borrowed from the kernel).
This makes SimNow work, since apparently though the codec is
present in Simnow, it is non functional.
Signed-off-by: Jordan Crouse <jordan.crouse@amd.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@904 f3766cd6-281f-0410-b1cd-43a5c92072e9
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@903 f3766cd6-281f-0410-b1cd-43a5c92072e9
byte-for-byte identical. That makes factoring out easier.
Fix a duplicated BIST save for K8.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@902 f3766cd6-281f-0410-b1cd-43a5c92072e9
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@901 f3766cd6-281f-0410-b1cd-43a5c92072e9
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@900 f3766cd6-281f-0410-b1cd-43a5c92072e9
arch/x86/i586/stage0.S to make it consistent with the other variants of
that code.
Clean up two superfluous rules from arch/x86/Makefile which were needed
before. That makefile change also fixes a latent bug which may have been
exposed by later additions to the tree.
Compile tested on all arches.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@899 f3766cd6-281f-0410-b1cd-43a5c92072e9
amd/Kconfig. Fix serengeti Makefile.
dbe62 was tested and works i.e. this does no harm.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@898 f3766cd6-281f-0410-b1cd-43a5c92072e9
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@897 f3766cd6-281f-0410-b1cd-43a5c92072e9
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@896 f3766cd6-281f-0410-b1cd-43a5c92072e9
m57sli) add incoherent ht chain support to stage1 as well.
dbe62 was tested and works i.e. this does no harm.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@895 f3766cd6-281f-0410-b1cd-43a5c92072e9
dbe62 was tested and works i.e. this does no harm.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@894 f3766cd6-281f-0410-b1cd-43a5c92072e9
23K, too large.
dbe62 was tested and works i.e. this does no harm.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@893 f3766cd6-281f-0410-b1cd-43a5c92072e9
dbe62 was tested and works i.e. this does no harm.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@892 f3766cd6-281f-0410-b1cd-43a5c92072e9
obsolete chip.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@891 f3766cd6-281f-0410-b1cd-43a5c92072e9
awful chip. But it builds.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@890 f3766cd6-281f-0410-b1cd-43a5c92072e9
version, with these typos, compiled.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@889 f3766cd6-281f-0410-b1cd-43a5c92072e9
dts and making the ops struct non-static.
This is the second pass on this patch, I have put the changes in that
Uwe requested, I hope I got them all. I have not heard back from Uwe yet
but this patch is urgent.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@888 f3766cd6-281f-0410-b1cd-43a5c92072e9
There are some interesting issues here. The enables for the various
devices are a global bitmask:
Define port_enable, (bit map): GFX(2,3), GPP(4,5,6,7)
But v3 would allow us to not have the bit mask. OTOH, we would end up
with 3 .dts files for the pcie ports for this enable; good or bad?
GOOD --> highly custom configuration possible for each port
BAD --> 3 .dts files
Part of the issue is that the link from the dts to the device operations
structure is done as follows:
struct device_operations sb600_usb2 = {
.id = {.type = DEVICE_ID_PCI,
{.pci = {.vendor = PCI_VENDOR_ID_ATI,
.device = PCI_DEVICE_ID_ATI_SB600_USB2}}},
And this structure is named in the .dts for that device_operations:
{
device_operations = "sb600_usb2";
};
requiring a different dts node for each set of device_operations.
The device tree compiler generates the code to create these connections
and puts that code into the the static_tree.c file.
Having a .dts file for each port gives us a lot of flexibility; but is
it too inconvenient? This is an unresolved problem; unhandled at present
for the *6* USB ports for the sb600.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@886 f3766cd6-281f-0410-b1cd-43a5c92072e9
My apologies.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@881 f3766cd6-281f-0410-b1cd-43a5c92072e9
Signed-off-by: Ronald G. Minnich <rminnch@gmail.com>
Acked-by: Ronald G. Minnich <rminnch@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@880 f3766cd6-281f-0410-b1cd-43a5c92072e9
- Coding style and whitespace fixes.
- Remove obsolete comments, fix incorrect ones.
- Use the full/canonical name of mainboards/vendors everywhere.
- Update the list of USB Debug capable chipsets from
http://www.coreboot.org/EHCI_Debug_Port.
- s/LB/CB/ for the CONSOLE_PREFIX kconfig option.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@879 f3766cd6-281f-0410-b1cd-43a5c92072e9
We need to figure out if we should just grow stage0. My inclination is
to say 'yes'.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@877 f3766cd6-281f-0410-b1cd-43a5c92072e9
mainboard that we learned with the serengeti that we needed. New
function in pnp that is for reading. new prototype in pnp.h. New
constants for ite8716f.
This board does not build yet; we are exercising code in k8 north that
the serengeti did not enable. More tomorrow.
Now that we have two boards under way we can hopefully see our way to
getting more put in. The 690 is the obvious next choice.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@876 f3766cd6-281f-0410-b1cd-43a5c92072e9
with buildrom. Informally acked by Ron.
Signed-off-by: Jordan Crouse <jordan.crouse@amd.com>
Acked-by: Jordan Crouse <jordan.crouse@amd.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@875 f3766cd6-281f-0410-b1cd-43a5c92072e9
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@874 f3766cd6-281f-0410-b1cd-43a5c92072e9
such as .note.this.that. These new note names were making builds
unbuildable on (e.g.) fc9.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@873 f3766cd6-281f-0410-b1cd-43a5c92072e9
moved to stage1 ROM code. Make the struct for nodeid/coreid generic to
x86. Create the functions for existing architectures are a model for
future architectures (VIA coming soon we hope).
Move includes so that things build correctly now.
This is actually a small patch that impacted a number of files due to
include order changes. This is build and boot tested on simnow and
build tested on geode.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@872 f3766cd6-281f-0410-b1cd-43a5c92072e9
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@871 f3766cd6-281f-0410-b1cd-43a5c92072e9
Far fewer warnings than before :-)
TODO: Document the DIMM_SETTINGS variable.
FIx up fidvid code.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@869 f3766cd6-281f-0410-b1cd-43a5c92072e9
AMP TinyGX still builds, this won't affect other platforms.
clean up 8111 stage1 code; add function to smbus,
memreset_setup_amd8111, for the 8111 specific parts of memreset.
include k8 .h to reduce warnings. Turn some things into functions (romcc
legacy cleanup) and put them in .c files.
simnow actually successfully gets through a reset cycle now.
Next is to fix the fidvid code.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@868 f3766cd6-281f-0410-b1cd-43a5c92072e9
some prints, and fixes a null pointer deref bug that has been in the
k8 code since the dawn of time.
We get here:
CPU 804 Mhz
Etherboot 5.4.3 (GPL) http://etherboot.org
Drivers: VIA-VELOCITY/PCI Images: ELF
Protocols: DHCP TFTP
Relocating _text from: [000100e0,000349c0) to [0007b720,000a0000)
Boot from (N)etwork or (Q)uit?
Probing pci nic...
Probing isa nic...
<sleep>
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@867 f3766cd6-281f-0410-b1cd-43a5c92072e9
and I committed it by accident.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@866 f3766cd6-281f-0410-b1cd-43a5c92072e9
multiple links. The way this was done in v2 was a big confusing; this way is
less so.
The changes are easy. Getting them right has been hard :-)
First, for a k8 north that has three links, you can name each one as follows:
pci0@18,0
pci1@18,0
pci2@18,0
We have to have the same pcidevfn on these because that is how the k8 works.
But the unit numbers (pci0, pci1, etc.) distinguish them.
The dts will properly generate a "v3 device code"
compatible static tree that puts the links in the right place in the
data structure.
The changes to dts are trivial.
As before, dts nodes with children are understood to be a bridge.
But what if there is a dts entry like this:
pci1@18,0 {/config/("northbridge/amd/k8/pci");};
This entry has no children in the dts.
How does dt compiler know it is a bridge? It can not know unless
we add information to the dts for that northbridge part.
To ensure that all bridge devices are detected, we support the following:
if a dts node for a device has a bridge property, e.g.:
{
device_operations = "k8_ops";
bridge;
};
The dt compiler will treat it as a bridge whether it has children or not.
Why would a device not have children? Because it might be attached to a
pci or other socket, and we don't know at build time if the socket is empty,
or what might be in the socket.
This code has been tested on dbe62 and k8 simnow, and works on each.
It is minimal in size and it does what we need. I hope it resolves our
discussion for now. We might want to improve or change the device code
later but, at this point, forward motion is important -- I'm on a deadline for
a very important demo Oct. 22!
Also included in this patch are new debug prints in k8 north.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@865 f3766cd6-281f-0410-b1cd-43a5c92072e9
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@864 f3766cd6-281f-0410-b1cd-43a5c92072e9
smbus.
Set up a global var variable called spd_inited. It is set when spd is
inited.
For simple cases, nothing is visible to initram main. For complex cases,
initram main can do the work and set this variable.
This compiles and runs on dbe62, which is actually meaningless since
dbe62
has not smbus, but hey ...
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@863 f3766cd6-281f-0410-b1cd-43a5c92072e9
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@862 f3766cd6-281f-0410-b1cd-43a5c92072e9
dtc only uses dev_fn as identifier for a PCI device. That gets us a name
collision if we have the same dev_fn combination on multiple buses.
Either we add a random unique ID to the struct name or we integrate the
path to the parent device as well.
I decided to go for integration of parent device path.
With the following device tree
/{
cpus {};
domain@0 {
bus@0 {
pci@0,0 {
};
pci@1,1 {
};
pci@f,0 {
bus@1 {
pci@0,0 {
};
};
};
};
};
};
we get the old names:
dev_root
dev_cpus
dev_domain_0
dev_bus_0
dev_pci_0_0
dev_pci_1_1
dev_pci_f_0
dev_bus_1
dev_pci_0_0 COLLISION!!!
and the new names:
dev_root
dev_cpus
dev_domain_0
dev_domain_0_bus_0
dev_domain_0_bus_0_pci_0_0
dev_domain_0_bus_0_pci_1_1
dev_domain_0_bus_0_pci_f_0
dev_domain_0_bus_0_pci_f_0_bus_1
dev_domain_0_bus_0_pci_f_0_bus_1_pci_0_0
Ron would like shorter names because they only have to be
machine-readable. That's left for another patch.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@860 f3766cd6-281f-0410-b1cd-43a5c92072e9
but that's not something we should rely on.
The new code is entirely rewritten, fixes a few missing constraints in
the asm and should be a lot more readable. However, the generated code
is NOT identical. The old code was broken because of the missing ecx
clobber constraint and it did not copy the stack back (ecx was zero at
the beginning of the copy-back loop and so the loop executed exactly
zero times).
So this is a genuine bug fix.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Ron writes:
wow! nice catch!
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
We also need disable_car_and_halt, which only disables car and halts,
for the APs (i.e. no need to copy stack back)
git-svn-id: svn://coreboot.org/repository/coreboot-v3@858 f3766cd6-281f-0410-b1cd-43a5c92072e9
r785 (move from explicit asm to implicit C) and unfortunately qemu never
triggered the bug, only real hardware did. That's because qemu will not
spew an error on access to RAM before RAM is enabled.
Thanks to Ron for bisecting this.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@857 f3766cd6-281f-0410-b1cd-43a5c92072e9
which point we hang:
Show all devs...
root(Root Device): enabled 1 have_resources 0 initialized 0
cpus: Unknown device path type: 0
cpus(): enabled 1 have_resources 0 initialized 0
apic_0(APIC: 00): enabled 1 have_resources 0 initialized 0
pci_1_0(PCI: 00:01.0): enabled 1 have_resources 0 initialized 0
pci_0_0(PCI: 00:00.0): enabled 1 have_resources 0 initialized 0
pci_4_0(PCI: 00:04.0): enabled 1 have_resources 0 initialized 0
pci_5_0(PCI: 00:05.0): enabled 1 have_resources 0 initialized 0
pci_18_0(PCI: 00:18.0): enabled 1 have_resources 0 initialized 0
ioport_2e(IOPORT: 2e): enabled 1 have_resources 0 initialized 0
domain_0(PCI_DOMAIN: 0000): enabled 1 have_resources 0 initialized 0
Phase 6: Initializing devices...
Phase 6: Root Device init.
Phase 6: PCI: 00:04.0 init.
The dts is quite incomplete and that is part of the problem. Doubtless
there are other problems :-)
But training is indeed working in simnow, and memory is working, and we
can return from disable_car as on the geode.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@855 f3766cd6-281f-0410-b1cd-43a5c92072e9
