BUG=b:62147763
Change-Id: I87e629a15de2f6882c1bf6f238931751db7515fd
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 3178bdc345
Original-Change-Id: Iba88fed972b847448e01fcfca8c7129d950244c2
Original-Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/19953
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/521040
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Add capability and location data for USB ports/devices via
_PLD and _UPC ACPI methods, which is utilized by Windows and
required by macOS.
Each slippy variant has slightly different USB port config;
data for falco and leon to be added once available
BUG=none
BRANCH=none
TEST=none
Change-Id: I0bde090fa65671806c58e5ee23d605cdc689a28a
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 39480c7204
Original-Change-Id: Icc3b5b1161f62ac0b840380679acafeff363cf45
Original-Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Original-Reviewed-on: https://review.coreboot.org/19967
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://chromium-review.googlesource.com/521039
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Add capability and location data for USB ports/devices via
_PLD and _UPC ACPI methods, which is utilized by Windows and
required by macOS.
All beltino variants use the exact same USB port layout.
BUG=none
BRANCH=none
TEST=none
Change-Id: I603fe9cacddb841592886724b260868323c95bb7
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 1186915c1f
Original-Change-Id: If5b540949ea071f7165876e12ac1ef50e62d2b22
Original-Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Original-Reviewed-on: https://review.coreboot.org/19966
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://chromium-review.googlesource.com/521038
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Add device/address stubs for XHCI USB ports 7, 10-13.
Stub data will be supplemented by board-specific info
added in subsequent commits.
BUG=none
BRANCH=none
TEST=none
Change-Id: I1836298d69bb87fab1cc024e94aab1eb3410075b
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: a672d155a2
Original-Change-Id: I7d2f93351435cccd62e8fe4d95ad3467aa09de69
Original-Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Original-Reviewed-on: https://review.coreboot.org/19965
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-on: https://chromium-review.googlesource.com/521037
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Add ACPI method GPLD to generate port location data when
passed visiblity info. Will be used by _PLD method in
board-specific USB .asl files.
BUG=none
BRANCH=none
TEST=none
Change-Id: I20ccd96b72a761001cc10c363ede04af19585e99
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 8b96fd2e5a
Original-Change-Id: If63d5637a0469eeace0d935cca961e8d04fdfb1a
Original-Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Original-Reviewed-on: https://review.coreboot.org/19964
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://chromium-review.googlesource.com/521036
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Add capability and location data for USB ports/devices via
_PLD and _UPC ACPI methods, which is utilized by Windows and
required by macOS.
Move inclusion of mainboard.asl after southbridge asl files
so scopes referenced in usb.asl are valid.
BUG=none
BRANCH=none
TEST=none
Change-Id: I9dac338bae16f7e8ef4b68561ab60009905712a0
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: c5bd8b359b
Original-Change-Id: I58ea0b43f7f2c2692630df3bdb06af92566c1202
Original-Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Original-Reviewed-on: https://review.coreboot.org/19963
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://chromium-review.googlesource.com/521035
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Add ACPI method GPLD to generate port location data when
passed visiblity info. Will be used by _PLD method in
board-specific USB .asl files.
BUG=none
BRANCH=none
TEST=none
Change-Id: I6193b5763b63dd5486163460d734f2789822c8f4
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: fa2df2a3f8
Original-Change-Id: Ib83660d6548112ceb6c75a31e5ce6c4a6041ccfb
Original-Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Original-Reviewed-on: https://review.coreboot.org/19962
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://chromium-review.googlesource.com/521034
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Port 0 is connected to SD-card reader.
Don't mark it as hot-plugable.
BUG=none
BRANCH=none
TEST=none
Change-Id: I3f7e4bd05d2619564408514a873d847e44cef5c0
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: a703393612
Original-Change-Id: I5d3d4c7541683a6c09aac47ca251a6dad23ad1ab
Original-Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Original-Reviewed-on: https://review.coreboot.org/19928
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://chromium-review.googlesource.com/521033
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
To unify the hwinfo handling along all Siemens MC boards the hwinfo
files have to be removed from the mainboard directory. They will be added
to cbfs in site-local/Makefile.inc.
BUG=none
BRANCH=none
TEST=none
Change-Id: I9cad8d637947c76327ffe1b22152e4d524f02424
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 7a3d6e1435
Original-Change-Id: Ia3dcb2e0118527b37aed872740273c4fa7004aef
Original-Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Original-Reviewed-on: https://review.coreboot.org/19982
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://chromium-review.googlesource.com/521032
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
The prior used RTC PCF8523 is replaced with RX6110SA on this mainboard.
Switch to the new RTC in Kconfig and adapt devicetree to the new chip.
BUG=none
BRANCH=none
TEST=none
Change-Id: I6aedee70a912bce4c5c1c651aa8d4c4363b0f632
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: cd37fef2e1
Original-Change-Id: I7c4911191cae254900f9a958da42ecd18497484c
Original-Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Original-Reviewed-on: https://review.coreboot.org/19979
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://chromium-review.googlesource.com/521031
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
The driver for the RTC RX6110SA is designed to be used with I2C bus.
This patch adds the possibility to use SMBus operations to access the
RTC. For this purpose the Kconfig switch RX6110SA_USE_SMBUS is added. It
is not enabled per default so that I2C will be used. One can set this
switch on board level to use SMBus instead.
BUG=none
BRANCH=none
TEST=none
Change-Id: I4bb997d09e0b1d573437a3be4f5945b5f969375a
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 57cbd21a52
Original-Change-Id: I4827ae2c544e8002399d94a1159acacd8176c5e9
Original-Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Original-Reviewed-on: https://review.coreboot.org/19978
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-on: https://chromium-review.googlesource.com/521030
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Modify the DPTF configuration on Eve to relax the severe throttling that
is currently applied and allow performance testing to see better results.
BUG=b:35581264
TEST=performance tests show better results and thermal tests still pass.
Change-Id: I3b2c10e68c6772453fbc16094e9d00d950d872b7
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 07a597feff
Original-Change-Id: I0838f4ec3026bc8bac814698043fa97cf6772cb4
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/19947
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://chromium-review.googlesource.com/521029
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Instead of having the SMI handler power off the touchscreen on the
way into suspend add power resource controls to the ACPI device so
the power is managed by the kernel instead of the BIOS.
BUG=b:35581264
TEST=manual testing on Eve to ensure that the touchscreen is still
functional at boot and after suspend/resume, and that it does not
draw power in suspend.
Change-Id: Ic1dd4ed8faab367347a4150c415a5cd40adb25f6
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: f124b88cfb
Original-Change-Id: Id9a98807d24bbc7dff32408f3d113f6fad5bc023
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/19946
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/521028
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Caching is a very architecture-specific thing, but most architectures
have a cache in general. Therefore it can be useful to have a generic
architecture-independent API to perform simple cache management tasks
from common code.
We have already standardized on the dcache_clean/invalidate naming
scheme that originally comes from ARM in libpayload, so let's just do
the same for coreboot. Unlike libpayload, there are other things than
just DMA coherency we may want to achieve with those functions, so
actually implement them for real even on architectures with
cache-snooping DMA like x86. (In the future, we may find applications
like this in libpayload as well and should probably rethink the API
there... maybe move the current functionality to a separate
dma_map/unmap API instead. But that's beyond scope of this patch.)
BUG=none
BRANCH=none
TEST=none
Change-Id: Id0ee072217b52fad2d68a1bd0f8dc69978e0fb1c
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: cd6b22f9a0
Original-Change-Id: I2c1723a287f76cd4118ef38a445339840601aeea
Original-Signed-off-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/19788
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Philippe Mathieu-Daud <philippe.mathieu.daude@gmail.com>
Reviewed-on: https://chromium-review.googlesource.com/521027
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
This patch adds a simple function that can be used to check if
CAR_GLOBALs are currently being read from CAR or from DRAM.
BUG=none
BRANCH=none
TEST=none
Change-Id: I625af4f75b86b11e95a249ff1c14b9b5e9b04b06
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: a92851939c
Original-Change-Id: Ib7ad0896a691ef6e89e622b985417fedc43579c1
Original-Signed-off-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/19787
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Philippe Mathieu-Daud <philippe.mathieu.daude@gmail.com>
Reviewed-on: https://chromium-review.googlesource.com/521026
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
The Tegra210 SoC never had a proper cpu_reset() implementation, so it's
pointless to pretend there is one. Most ARM SoCs/boards only define
hard_reset() at the moment anyway, so let's stick with that.
BUG=none
BRANCH=none
TEST=none
Change-Id: Ifeb6b0b2a4417bdb13908ceb0aa4e382b40a91c5
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: c25b2a18fa
Original-Change-Id: I40f39921fa99d6dfabf818e7abe7a5732341cf4f
Original-Signed-off-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/19786
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Reviewed-by: Philippe Mathieu-Daud <philippe.mathieu.daude@gmail.com>
Reviewed-on: https://chromium-review.googlesource.com/521025
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
coreboot and libpayload currently use completely different code to
perform a full cache flush on ARM64, with even different function names.
The libpayload code is closely inspired by the ARM32 version, so for the
sake of overall consistency let's sync coreboot to that. Also align a
few other cache management details to work the same way as the
corresponding ARM32 parts (such as only flushing but not invalidating
the data cache after loading a new stage, which may have a small
performance benefit).
BUG=none
BRANCH=none
TEST=none
Change-Id: I36773b526de93ec2367bc7c826e63a68bb8ef6ef
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: baa3e70084
Original-Change-Id: I9e05b425eeeaa27a447b37f98c0928fed3f74340
Original-Signed-off-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/19785
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/521024
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
BUG=none
BRANCH=none
TEST=none
Change-Id: I2649d7176b88eef5dad66dc839f6f8d2dd496926
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: e801fcb421
Original-Change-Id: Ib53f591e5c8b03cd45b3fbd3db36ea2c28e4e060
Original-Signed-off-by: Martin Roth <martinroth@google.com>
Original-Reviewed-on: https://review.coreboot.org/19951
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://chromium-review.googlesource.com/521023
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Specification says to do CAR teardown as part of AmdInitPost().
Move initializing the final AGESA heap storage to AmdInitEnv()
so that its work is not lost even if AMD_DISABLE_STACK does
invalidation without writeback.
BUG=none
BRANCH=none
TEST=none
Change-Id: I56a7f785cfcd1b4867ec31aba27fcda532700632
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 4c1e41c636
Original-Change-Id: Icf0ec74c390e60122d0b312b5f09f46bb930e085
Original-Signed-off-by: Kysti Mlkki <kyosti.malkki@gmail.com>
Original-Reviewed-on: https://review.coreboot.org/19270
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Philippe Mathieu-Daud <philippe.mathieu.daude@gmail.com>
Reviewed-on: https://chromium-review.googlesource.com/521022
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
As the comment above the change indicates, and per ACPI spec,
_DSS has one argument.
BUG=none
BRANCH=none
TEST=none
Change-Id: I54e32bf6a81cf577a6a39166bce7e781bcbe0fe6
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 17b1a69c52
Original-Change-Id: Ic05832d412cd0c89ed3a275c4db694a9118dac28
Original-Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Original-Reviewed-on: https://review.coreboot.org/19952
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Philippe Mathieu-Daud <philippe.mathieu.daude@gmail.com>
Original-Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://chromium-review.googlesource.com/517790
Via/VX800 was the last chip not defining it.
BUG=none
BRANCH=none
TEST=none
Change-Id: I4ce6bc9a04a218d44e9da824c7ad3a54a43d4354
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: e63ba791dd
Original-Change-Id: Idd03f48bed881a5846b1bb3bf29254450d6cff3b
Original-Signed-off-by: Nico Huber <nico.h@gmx.de>
Original-Reviewed-on: https://review.coreboot.org/19748
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/517938
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Get rid of mainboard_io_trap_handler.
The only purpose is to enable tp-smapi, but is already done on all
boards in h8_enable, as of devicetree setting config0.
BUG=none
BRANCH=none
TEST=none
Change-Id: If248d0142568db0f89b18225335bd8f336c55570
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 8953d4a137
Original-Change-Id: I33fd829a7e34aefa8f76ca6020cc8e802f7aab17
Original-Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Original-Reviewed-on: https://review.coreboot.org/19790
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://chromium-review.googlesource.com/517937
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Instead of assuming the mapping of dimm number to SPD SMBus address,
allow the mainboard to provide its own mapping. That way, global
resources of empty SPD contents aren't wasted in order to address
a dimm on a mainboard that doesn't meet the current assumption.
BUG=none
BRANCH=none
TEST=none
Change-Id: I1ef87d18b30192be730805238df62ff81f130339
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: dd82edc388
Original-Change-Id: Id0e79231dc2303373badaae003038a1ac06a5635
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/19915
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Furquan Shaikh <furquan@google.com>
Original-Reviewed-by: Naresh Solanki <naresh.solanki@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/517936
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
GPP_C2 is being used as strapping option, so
should not be set to NF. Signal was floating
previously, which can lead to an assertion of
smbalert#.
BUG=b:37681121, b:35775024
BRANCH=None
TEST=powerd_dbus_suspend and ensure stays in suspend
Change-Id: Ife5a3d8c442e3f29c2dc549b9f6887d526cbf8f2
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: c96f757af1
Original-Change-Id: I68091206014621419b886b723a5681541be989bc
Original-Signed-off-by: Shelley Chen <shchen@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/19904
Original-Reviewed-by: Furquan Shaikh <furquan@google.com>
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-on: https://chromium-review.googlesource.com/517935
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
This should allow Jenkins to parse the build failures when Kconfig
generates an error.
BUG=none
BRANCH=none
TEST=none
Change-Id: I59fa7e6ca98d6dd4ddd9f582cd96e27c119cdac6
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 16c49b5ff5
Original-Change-Id: I5f9083c346ac7b6502f854b7e1f1054e81954d76
Original-Signed-off-by: Martin Roth <martinroth@google.com>
Original-Reviewed-on: https://review.coreboot.org/19861
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://chromium-review.googlesource.com/517934
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
The deprecated LATE_CBMEM_INIT function is renamed:
set_top_of_ram -> set_late_cbmem_top
Obscure term top_of_ram is replaced:
backup_top_of_ram -> backup_top_of_low_cacheable
get_top_of_ram -> restore_top_of_low_cacheable
New function that always resolves to CBMEM top boundary, with
or without SMM, is named restore_cbmem_top().
BUG=none
BRANCH=none
TEST=none
Change-Id: I0912069553813210587354ce181942f5974eed4b
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 70d92b9465
Original-Change-Id: I61d20f94840ad61e9fd55976e5aa8c27040b8fb7
Original-Signed-off-by: Kysti Mlkki <kyosti.malkki@gmail.com>
Original-Reviewed-on: https://review.coreboot.org/19377
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Philippe Mathieu-Daud <philippe.mathieu.daude@gmail.com>
Reviewed-on: https://chromium-review.googlesource.com/517933
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Add more fine-grained details about what device caused the PME wake
event. This requires checking the PME status bit (bit 15) in PCI PM
control and status register for the PCI device.
BUG=b:37088992
TEST=Verifed that XHCI wake source was identified correctly:
135 | 2017-05-25 15:28:17 | ACPI Enter | S3
136 | 2017-05-25 15:28:26 | ACPI Wake | S3
137 | 2017-05-25 15:28:26 | Wake Source | PME - XHCI | 0
Change-Id: Ieef07a972d2a610284df082109a5bda59ab10dba
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: ef8bb9136e
Original-Change-Id: I6fc6284cd04db311f1f86b8a86d0bb708392e5d5
Original-Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/19925
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-on: https://chromium-review.googlesource.com/517932
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
This is required to add wake sources for PCIE PME events.
BUG=b:37088992
Change-Id: I46f4b244510ba5201566a4cd2c7e2e205b065137
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 1cf7f86d92
Original-Change-Id: Ideecdf133908b0819d7d993e1c7df1a6578cb77d
Original-Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/19924
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Philippe Mathieu-Daud <philippe.mathieu.daude@gmail.com>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/517931
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Add wake sources for PME events generated by different devices.
BUG=b:37088992
Change-Id: I05b212d6043b50588d54d7069db76ce89f3459e5
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: b858157dba
Original-Change-Id: I25098f489f401148171c235cb341f6e7bb2b635b
Original-Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/19923
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/517930
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Not all systems have sizeof(time_t) == sizeof(long), so
cast the delta here to a long to match the %ld format.
BUG=none
BRANCH=none
TEST=none
Change-Id: Ic398f319b1711f32e4e2c0b579d2fc858084f714
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: a8ca03223a
Original-Change-Id: If235577fc35454ddb15043c5a543f614b6f16a9e
Original-Signed-off-by: Mike Frysinger <vapier@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/19902
Original-Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-on: https://chromium-review.googlesource.com/517929
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
This patch fix rk_mipi_dsi_phy_init error return.
BUG=none
BRANCH=none
TEST=none
Change-Id: I731277cde56270bcf18f97dc5c9a0eacbaa12121
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 5be0b2e03d
Original-Change-Id: Ie260975ad6ed26c37aa8bb65dfcef4db2407a2da
Original-Signed-off-by: Nickey Yang <nickey.yang@rock-chips.com>
Original-Reviewed-on: https://review.coreboot.org/19903
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/517928
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
BUG=none
BRANCH=none
TEST=none
Change-Id: I45a8b5be4e26b1edfd42bac86daf1e98b19bd781
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 6b697ef207
Original-Change-Id: Iac4cdb003b2fe967b303c1f8e0eeb61673a02858
Original-Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Original-Reviewed-on: https://review.coreboot.org/19930
Original-Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Original-Tested-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://chromium-review.googlesource.com/517927
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
hugo has no need to write there, it should only write to the
output directory.
BUG=none
BRANCH=none
TEST=none
Change-Id: Icac77298ae86d06bdeb350706e207c3e6c4d664f
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: dc5eea1cfa
Original-Change-Id: Ie320f5017feccfa2e9ecba3c802e040487b44d67
Original-Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Original-Reviewed-on: https://review.coreboot.org/19929
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://chromium-review.googlesource.com/517926
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
1. Do not enable touchscreen device by default in gpio configuration.
2. Select use of PowerResource for touchscreen device in devicetree so
that the ACPI subsystem can take care of powering on/off the
device. When system enters suspend, touchscreen device is powered off
and on resume, it is powered back on.
BUG=b:62028489
TEST=Verified 100 cycles of suspend-resume. Touchscreen still works on
poppy.
Change-Id: Ibae8907f260b50eb0d1283f26294fb73e963d051
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 73108ded48
Original-Change-Id: Ia0bebc7259b10cc60a9fa5b53542dfdd9685663e
Original-Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/19829
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-on: https://chromium-review.googlesource.com/517925
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
www.coreboot.org/Documentation is now built with hugo (www.gohugo.io)
based on files in this repo's /Documentation directory.
Also clarify that new additions to Documentation are under CC-BY 4.0 terms.
BUG=none
BRANCH=none
TEST=none
Change-Id: Iedadababa4129d983118eb9a59f93d3fa3a4bb0c
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 04edaefad7
Original-Change-Id: I000e15b29a182bb88b40de3d0178bf8cc54ba8af
Original-Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Original-Reviewed-on: https://review.coreboot.org/19881
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Reviewed-on: https://chromium-review.googlesource.com/517924
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Namely png (images) and eot, ttf, woff (fonts)
BUG=none
BRANCH=none
TEST=none
Change-Id: I34654dcc6c7f4b6eae00c69c55d58b6b012fce20
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 9ec25f7678
Original-Change-Id: I41e773c0adab796876a3b1e91e089ae89cbb04df
Original-Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Original-Reviewed-on: https://review.coreboot.org/19880
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Reviewed-on: https://chromium-review.googlesource.com/517923
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Implement GPIO ACPI AML generating functions that can be called by
coreboot drivers to generate GPIO manipulation code in AML. Following
API functions are implemented:
1. acpigen_soc_read_rx_gpio
2. acpigen_soc_get_tx_gpio
3. acpigen_soc_set_tx_gpio
4. acpigen_soc_clear_tx_gpio
In addition to the API functions above, helper functions are added to
gpio.asl to set/clear/get Tx value of GPIO.
BUG=b:62028489
Change-Id: Ie79dcb9c4b57bfe435d173310025577a947509ac
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: a6f0b2754b
Original-Change-Id: I77e5d0decd8929a922d06b02312378f092551667
Original-Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/19828
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-on: https://chromium-review.googlesource.com/515866
Commit-Ready: Shelley Chen <shchen@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Shelley Chen <shchen@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Instead of storing inverted-colored bitmaps,
invert drawing of text bitmap on the fly by adding
an invert parameter down to libpayload. Merging
pivot and invert fields into flags field.
BUG=b:35585623
BRANCH=None
TEST=Make sure compiles successfully
Change-Id: Ie397160b54f488abd7260332ee26d0b5140584bb
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: d635506fa7
Original-Change-Id: Ide6893a26f19eb2490377d4d53366ad145a9e6e3
Original-Signed-off-by: Shelley Chen <shchen@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/19698
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://chromium-review.googlesource.com/515865
Commit-Ready: Shelley Chen <shchen@chromium.org>
Tested-by: Shelley Chen <shchen@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Should result in a tiny speed bump in raminit since those addresses
are not checked for present DIMMs.
Checked in schematics of both Thinkpad X60 and T60 and tested to
configure raminit correctly for all DIMMs populated on X60.
BUG=none
BRANCH=none
TEST=none
Change-Id: Ib52cde02578aa34de55be6e9b482ba47019b9809
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 000cc598cb
Original-Change-Id: I56c4f3176541bc75a8de3aac9f87526a77fc819b
Original-Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Original-Reviewed-on: https://review.coreboot.org/19862
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://chromium-review.googlesource.com/515864
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
BUG=none
BRANCH=none
TEST=none
Change-Id: I355a6b7527743f863e1fa34d52bca28506975aa9
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 36dafd88bc
Original-Change-Id: Ia44097f32f74ffd749219415984224ce33d9252b
Original-Signed-off-by: Nico Huber <nico.h@gmx.de>
Original-Reviewed-on: https://review.coreboot.org/19816
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://chromium-review.googlesource.com/515863
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
It seems that the BootROM on the RK3399 overwrites some of the earlier
parts of SRAM, including the PRERAM_CBMEM_CONSOLE area. Now that we have
a persistent CBMEM console we want that area to survive in case of an
early (pre-CBMEM) reboot, so shuffle the layout around a bit to move it
further back. (This reduces the stack size to 12KB which should still be
way more than enough.)
BUG=none
BRANCH=none
TEST=none
Change-Id: Iac2a886490fbd53c9655ea9edb5df89bae9a37b2
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 34dba35831
Original-Change-Id: Ifc1e568cda334394134bba9eba75088032d2ff13
Original-Signed-off-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/19784
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Furquan Shaikh <furquan@google.com>
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://chromium-review.googlesource.com/514193
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Soraka uses OV 13858 sensor. Hence update the same.
BUG=none
BRANCH=none
TEST=none
Change-Id: If48f4c2411f2450f2d617b342c587ccf5675a51e
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: b25b2329a9
Original-Change-Id: I4dd39a25da47e379cca3f8748250b3ce1ff61e50
Original-Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com>
Original-Reviewed-on: https://review.coreboot.org/19639
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Rajneesh Bhardwaj <rajneesh.bhardwaj@intel.com>
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Original-Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://chromium-review.googlesource.com/514192
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
It could end up not initialized which causes it not to build with
clang.
BUG=none
BRANCH=none
TEST=none
Change-Id: I295a03b36c881c157fd8ae00cace1686d67089ee
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 37689fae38
Original-Change-Id: I3be9477d836123aaa87c9bebb41c1ec34689a771
Original-Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Original-Reviewed-on: https://review.coreboot.org/19736
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Reviewed-by: Philippe Mathieu-Daud <philippe.mathieu.daude@gmail.com>
Original-Reviewed-by: Nico Huber <nico.h@gmx.de>
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://chromium-review.googlesource.com/514191
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Though SPD is rightly selected (i.e., H9CCNNNBKTALBR-NUD),
it displays wrong part number during boot in coreboot logs.
So correct part number info within the SPD.
TEST= Build for Soraka & make sure part number is rightly printed.
Change-Id: I6ab2b81223364c7e48e9d64e080f459c27843d09
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 1d407cceaf
Original-Change-Id: I67f676fb6ee9d685fa7aa41fdc4b00355e6d33c7
Original-Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com>
Original-Reviewed-on: https://review.coreboot.org/19692
Original-Reviewed-by: Furquan Shaikh <furquan@google.com>
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-on: https://chromium-review.googlesource.com/514190
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Now that all platforms are updated to provide spi bus map, there is no
need to keep the spi_setup_slave as a weak symbol.
BUG=b:38430839
Change-Id: I9b4b8a600b5b6de3b2ec9956f24f09eaa4b2a321
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: dd8d24759d
Original-Change-Id: I59b9bbb5303dad7ce062958a0ab8dee49a4ec1e0
Original-Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/19781
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-on: https://chromium-review.googlesource.com/514189
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
No mainboard is actually using this SoC. Remove the code for this SoC
for now.
BUG=b:38430839
Change-Id: If7034ff7d092b2935519b54c6267abe9ea0f7f21
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 53bbf87a4c
Original-Change-Id: Ia35986dffda8bbd76305ef5abab6ae81cc154b0f
Original-Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/19824
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-on: https://chromium-review.googlesource.com/514188
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
This is in preparation to get rid of the strong spi_setup_slave
implemented by different platforms.
BUG=b:38430839
Change-Id: Ia7c95879b7c96f8ed0913959f587f7deefe62dec
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 12eca76469
Original-Change-Id: I2a789cff40fb0e6bd6d84565531d847afb3f8bed
Original-Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/19780
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Philippe Mathieu-Daud <philippe.mathieu.daude@gmail.com>
Reviewed-on: https://chromium-review.googlesource.com/514187
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
This is in preparation to get rid of the strong spi_setup_slave
implemented by different platforms.
BUG=b:38430839
Change-Id: I269ad36b81a4365807d036038d16de2d5077f253
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 2cd03f1696
Original-Change-Id: I23c1108c85532b7346ff7e0adb0ac90dbf2bb2cc
Original-Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/19779
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Philippe Mathieu-Daud <philippe.mathieu.daude@gmail.com>
Reviewed-on: https://chromium-review.googlesource.com/514186
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
This is in preparation to get rid of the strong spi_setup_slave
implemented by different platforms.
BUG=b:38430839
Change-Id: Ib2484bdf3e8a45eefc46c71ae4c52fb7d07ff6bb
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 2d9a99535d
Original-Change-Id: Id3f05a2ea6eb5e31ca607861973d96b507208115
Original-Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/19778
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Philippe Mathieu-Daud <philippe.mathieu.daude@gmail.com>
Reviewed-on: https://chromium-review.googlesource.com/514185
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
