Relevant changes (commit 250b2ec):
* Fix a bug for ME6 Ignition images.
* Fix signature checking for ME11 and later.
* Add command line arguments.
* Add an option to relocate the FTPR partition to the top of the
ME region, recovering most of the ME region space.
* Print the image minimum size.
* Add write boundary checks, to prevent writes on other regions
in case of bugs.
The new changes have been tested on multiple platforms by the
me_cleaner users. They have been tested also on the author's
X220T with coreboot, where the ME region has been shrinked up to
84 kB without any issue.
BUG=none
BRANCH=none
TEST=none
Change-Id: I8c4e8474dd3ae4fb48ea2423ce4fcf39e527c191
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: e38f85915f
Original-Change-Id: I3bd6b4cba9f5eebc3cd4892dd9f188744a06c42b
Original-Signed-off-by: Nicola Corna <nicola@corna.info>
Original-Reviewed-on: https://review.coreboot.org/18473
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Reviewed-on: https://chromium-review.googlesource.com/449831
This reverts commit fec8872c9d.
The commit introduced a regression which is causing MC4 failures
when 8 RDIMMs are populated in a configuration with a single CPU
package. Using just 4 RDIMMs, the failure does not occur.
After reverting the commit, I tested configurations with
1 CPU (8x8=64GB) and 2 CPU packages (16x8=128GB) using an
Opteron 6276. The MC4 failures did not occur anymore.
BUG=none
BRANCH=none
TEST=none
Change-Id: I0a508bff03899c8b7bd7429bce653a7bea94bef0
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 610d1c67b2
Original-Change-Id: Ic6c9de84c38f772919597950ba540a3b5de68a65
Original-Signed-off-by: Daniel Kulesz <daniel.ina1@googlemail.com>
Original-Reviewed-on: https://review.coreboot.org/18369
Original-Tested-by: build bot (Jenkins)
Original-Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Original-Reviewed-by: Timothy Pearson <tpearson@raptorengineering.com>
Reviewed-on: https://chromium-review.googlesource.com/449827
The newly assigned ACPI ID for coreboot is 'BOOT'
http://www.uefi.org/acpi_id_list
Use this new range of ACPI IDs of "BOOTxxxx" for coreboot specific
ACPI objects instead of the placeholder range of "GOOGCBxx".
BUG=none
BRANCH=none
TEST=none
Change-Id: Ia3bfdec7652d4cf7c8647a7e3b0a1a324666b0af
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 59eddac6ad
Original-Change-Id: I10b30b5a35be055c220c85b14a06b88939739a31
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/18521
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://chromium-review.googlesource.com/449826
Fix a typo that was introduce in commit 696ebc2d (Broadwell/Sata:
Add support for setting IOBP registers for Ports 2 and 3.) [1].
Setting one of the SATA port 3 IOBP setting was using the value from
the port 2 register.
On the purism/librem13 (on which SATA port 3 is tested), this change
doesn't seem to affect anything, as that typo wasn't exhibiting any
visible problems anyways.
[1] https://review.coreboot.org/18408
BUG=none
BRANCH=none
TEST=none
Change-Id: I872b03d4d4d28ae77d1cfe315da6a336c555817b
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 601aa313a6
Original-Change-Id: I3948def5c0588791009c4b24cbc061552d9d1d48
Original-Signed-off-by: Youness Alaoui <youness.alaoui@puri.sm>
Original-Reviewed-on: https://review.coreboot.org/18514
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-by: Philippe Mathieu-Daud <philippe.mathieu.daude@gmail.com>
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://chromium-review.googlesource.com/449825
Follow commit 7676730 (mb/lenovo/x60: Remove PCI reset code from
romstage). The PCI reset was copied from code specific for Roda
RK886EX and Kontron 986LCD-M. It is not needed on the MacBook.
BUG=none
BRANCH=none
TEST=none
Change-Id: I1a8fb6acddf19dfe8cbfcc9ef74684d8b7ac6950
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: a154a910cb
Original-Change-Id: I22dac962e8079732591f9bc134c1433f5c29ff4e
Original-Signed-off-by: Axel Holewa <mono-for-coreboot@donderklumpen.de>
Original-Reviewed-on: https://review.coreboot.org/18502
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Nico Huber <nico.h@gmx.de>
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://chromium-review.googlesource.com/449824
struct dimm_info has all the parameter types defined in stdint.h
file. So including it.
BUG=none
BRANCH=none
TEST=Build and boot KBLRVP
Change-Id: Ifca96aea794f3bdb6e150bb5e61301d0169e5e8e
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: c16d389363
Original-Change-Id: I707523749ecf415e993b460f9613eae7be859c34
Original-Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com>
Original-Reviewed-on: https://review.coreboot.org/18471
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Philippe Mathieu-Daud <f4bug@amsat.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/449822
Save SMBIOS memory information from FSP MEM_INFO_DATA_HOB in CBMEM.
Add function dimm_info_fill() which populates SMBIOS memory
information from FSP MEM_INFO_DATA_HOB data.
BUG=chrome-os-partner:61729
BRANCH=none
TEST=Build and boot KBLRVP to verify the type 17 DIMM info coming in
SMBIOS table from Kernel command "dmidecode".
Change-Id: I489ff93622c18183115b9d7a0cb62a22a96bdc3e
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: e13b77564f
Original-Change-Id: I0fd7c9887076d3fdd320fcbdcc873cb1965b950c
Original-Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com>
Original-Reviewed-on: https://review.coreboot.org/18418
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/449821
Add the MemInfoHob.h provided by FSP v1.6.0 for aid in parsing the
MEM_INFO_DATA_HOB.
BUG=chrome-os-partner:61729
BRANCH=none
TEST=Build and boot KBLRVP
Change-Id: I0f6d691fcc4c3be900108dda8fb1d8cc7d3c3144
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 9e54978f6e
Original-Change-Id: Ia2b528ba4d9f093006cc12ee317d02e7f3e83166
Original-Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com>
Original-Reviewed-on: https://review.coreboot.org/18326
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/449820
thinkpad_acpi expects a SSMS method to turn on/off the mute LED
and a MMTS method to turn on/off the microphone mute LED. With
these methods implemented the driver can correctly sync the LEDs
with the corresponding statuses.
There seems to be two different bits to mute the audio in the
Lenovo H8 EC:
* AMUT, used internally (for example to disable the audio before
entering S3).
* ALMT, controllable by the OS, which also toggles the mute LED
(if present).
Tested on a X220T and on a X201.
BUG=none
BRANCH=none
TEST=none
Change-Id: I6a33511266f67aa2337b83673ea7a990f33df6a9
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 068edc1c52
Original-Change-Id: I578f95f9619a53fd35f8a8bfe5564aeb6c789212
Original-Signed-off-by: Nicola Corna <nicola@corna.info>
Original-Reviewed-on: https://review.coreboot.org/18329
Original-Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
Original-Tested-by: build bot (Jenkins)
Reviewed-on: https://chromium-review.googlesource.com/449819
Currently, the USB ports are still powered during S3, so turning
them off may reduce the power consumption.
Note that, when the USB Always on feature is enabled, the USB
ports are always powered, regardless of the USBP state.
This patch also disables the audio, as it might consume some
power or generate some noise.
Both the USB power and the audio are reenabled by coreboot during
the poweron.
BUG=none
BRANCH=none
TEST=none
Change-Id: Iab4aff2c38ee494a5db3b0804f154ecbd4955f75
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 435d307415
Original-Change-Id: If0431b1315fffef2e372e7023f830a66bb7fddae
Original-Signed-off-by: Nicola Corna <nicola@corna.info>
Original-Reviewed-on: https://review.coreboot.org/18464
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
Reviewed-on: https://chromium-review.googlesource.com/449818
On the models that support it (like the X220) the LED pulses, on
the others (like the X201) the LED powers off.
BUG=none
BRANCH=none
TEST=none
Change-Id: Ibcb9d2bfe1c1d93d3af828f1eac7438f38ae2d56
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: b1ffff7dab
Original-Change-Id: I2ac7dbc30609179e4ca5fc0a7b06763431fe3344
Original-Signed-off-by: Nicola Corna <nicola@corna.info>
Original-Reviewed-on: https://review.coreboot.org/18325
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
Reviewed-on: https://chromium-review.googlesource.com/449817
thinkpad_acpi expects a MHKG method which returns the current
state of the tablet mode switch shifted left by 3. If such
method is not found, subsequent laptop/tablet mode events are
ignored.
Tested on a X220T.
BUG=none
BRANCH=none
TEST=none
Change-Id: I0f07edd24cb8edef45ae62df7edc06fcc1aeb68c
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 47f87bd93f
Original-Change-Id: Ic9ffea2ffe507b3692d1dd7411c52b813ec32146
Original-Signed-off-by: Nicola Corna <nicola@corna.info>
Original-Reviewed-on: https://review.coreboot.org/18328
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
Reviewed-on: https://chromium-review.googlesource.com/449816
This timeout is probably needed on all devices with Lenovo H8 embedded
controllers so set the default there.
BUG=none
BRANCH=none
TEST=none
Change-Id: I8c622291d18ebe5433d10f839abb76dfbf92fead
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: f77d6ba911
Original-Change-Id: I830ab1894f7c0f10f55c82e398becf44d810852d
Original-Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Original-Reviewed-on: https://review.coreboot.org/18274
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
Reviewed-on: https://chromium-review.googlesource.com/449815
Since version 9332965 "serialio: Support for mmap serial ports", SeaBIOS
supports memory mapped serial ports. This patch automatically configures
SeaBIOS when the Hudson UART is enabled.
BUG=none
BRANCH=none
TEST=none
Change-Id: I3a0b85f4e566c77847cc201c827a45c4f74b19e1
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 77ced402fb
Original-Change-Id: I072f6a957df7e143d790783546b0725bcd597d9c
Original-Signed-off-by: Ricardo Ribalda Delgado <ricardo.ribalda@gmail.com>
Original-Reviewed-on: https://review.coreboot.org/18025
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://chromium-review.googlesource.com/449814
RAMD_ID_1 moves to PAD_DSI_TE and RAM_ID_2 moves to PAD_RDP1_A on Rowan.
BUG=chrome-os-partner:62672
BRANCH=none
TEST=emerge-rowan coreboot
Change-Id: I64fd29de607a0b360d355fd3724e3a649adc658b
Signed-off-by: Yidi Lin <yidi.lin@mediatek.com>
Reviewed-on: https://chromium-review.googlesource.com/448397
Reviewed-by: Julius Werner <jwerner@chromium.org>
The differential signal of DQS need keep low
level before gate training. RPULL will connect
4Kn from PADP to VSS and a 4Kn from PADN to
VDDQ to ensure it.But if it have PHY side ODT
connect at this time,it will change the DQS
signal level.So it need disable PHY side ODT
when do gate training.
BRANCH=None
BUG=None
TEST=boot from bob
Change-Id: I33cf743c3793a2765a21e5121ce7351410b9e19d
Signed-off-by: Lin Huang <hl@rock-chips.com>
Reviewed-on: https://chromium-review.googlesource.com/448278
Commit-Ready: Caesar Wang <wxt@rock-chips.com>
Tested-by: Caesar Wang <wxt@rock-chips.com>
Reviewed-by: Derek Basehore <dbasehore@chromium.org>
Gru/Kevin use the 933M(actually 928M for better jitter) as max sdram freq,
while bob would use 800M.
It's normal some variants can't meet 928M SI requirement and hence want
use a lower freq as spec.
BUG=chrome-os-partner:61001
BRANCH=gru
TEST=check dpll is 800M on bob
Change-Id: I46afba8d091f1489feeb20cafc44decaa81601fc
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
Signed-off-by: Shunqian Zheng <zhengsq@rock-chips.com>
Reviewed-on: https://chromium-review.googlesource.com/420208
Reviewed-by: Julius Werner <jwerner@chromium.org>
Commit-Queue: Shasha Zhao <Sarah_Zhao@asus.com>
Tested-by: Shasha Zhao <Sarah_Zhao@asus.com>
(cherry picked from commit eba5dff79eeedae5ff608d2d8d297ccf9c13cb55)
Reviewed-on: https://chromium-review.googlesource.com/448277
Reviewed-by: Derek Basehore <dbasehore@chromium.org>
The cr50 part on reef is connected to the SoC's UART lines. However,
when the tx signal is low it causes an interrupt to fire on cr50.
Therefore, keep the tx signal high in suspend state so that it doesn't
cause an interrupt storm on cr50 which prevents cr50 from sleeping.
BUG=chrome-os-partner:63283
BRANCH=reef
TEST=s0ix no longer causes interrupt storm on cr50. Power consumption
normal.
Change-Id: I38a14abff2f619b2b11a8f3a12ce54f61028fb48
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 6295b8a57a
Original-Change-Id: Idaeb8e4427c1cec651122de76a43daa15dc54d0f
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/18491
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://chromium-review.googlesource.com/446843
Apply tuning for the PCH I2C buses on Eve based on rise/fall time
measurements that were done with a scope.
BUG=chrome-os-partner:59686
BRANCH=none
TEST=Manual testing on Eve P1 to verify that all devices on I2C
buses are still functional. Post-tuning measurement will be done
once a new firmware is released.
Change-Id: If6d7f8c77504c281bc4c0788ec0c5aa5c2607ed2
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: d4d6ba180d
Original-Change-Id: I3d70ff455a20ecda374d7e7fa6cd3ab15e7f2621
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/18487
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://chromium-review.googlesource.com/446842
This patch tries to clean the code by:
o removing duplication of LPC GPIO pads
o removing incorrect definitions from devicetree
o removing irrelevant entries from FMD file
Also adds vital defaults in Kconfig so it is possible to build an image.
BUG=none
BRANCH=none
TEST=none
Change-Id: I31e2bda3b511f14fc46493f2d669b26a0329082d
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 6a489237d5
Original-Change-Id: Id9913f3b053189166392271152ce5300d82a7de8
Original-Signed-off-by: Andrey Petrov <andrey.petrov@intel.com>
Original-Reviewed-on: https://review.coreboot.org/18479
Original-Tested-by: build bot (Jenkins)
Reviewed-on: https://chromium-review.googlesource.com/446841
This fixes a warning that the new toolchain generates.
BUG=none
BRANCH=none
TEST=none
Change-Id: I110558801c33c2d82d56b8fd0a65b10f0e161605
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 37e30aa624
Original-Change-Id: Idf46026729a474323e74a5cf7a156bf5bc8cf026
Original-Signed-off-by: Jonathan Neuschfer <j.neuschaefer@gmx.net>
Original-Reviewed-on: https://review.coreboot.org/18485
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Original-Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://chromium-review.googlesource.com/446840
BUG=chrome-os-partner:62967
BRANCH=None
TEST=Verified that touchscreen works on power-on and after
suspend-resume as well.
Change-Id: If0956204a6c6c266ea2383e29d8738b282caeb2e
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 613350897d
Original-Change-Id: Id674cbcc2d524a6ed2883bf9f0e9e076890f9a85
Original-Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/18466
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/446839
This change is based on the following commit:
3aa91dc payloads/seabios: Add "git revision" to the SeaBIOS version menu
BUG=none
BRANCH=none
TEST=none
Change-Id: Iaee9f1240d01b1055b05320b2cfb2263d819f409
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 08cf195f4c
Original-Change-Id: I9987e3673e70b5cb20173d1ddff6060f42a5374a
Original-Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo@no-log.org>
Original-Reviewed-on: https://review.coreboot.org/18352
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://chromium-review.googlesource.com/446392
On my Thinkpad with an H8-compatible ENE KB9012 EC (GDHT92WW 1.52), when
the battery is nearly full and we switch from battery to AC by plugging
in the cable, the current rate will not drop to 0 immediately, but the
discharging state is cleared immediately.
This leads to the code trying to process an invalid rate value >0x8000,
leading to a displayed rate of >1000W.
This patch changes the logic to deal with these corner cases.
BUG=none
BRANCH=none
TEST=none
Change-Id: Ib0ec4d6bd5ecc128485e89449fca8021c58dd272
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 9b798d7904
Original-Change-Id: Ideb588d00757f259792e5ae97729e371b63a096c
Original-Signed-off-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de>
Original-Reviewed-on: https://review.coreboot.org/18349
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://chromium-review.googlesource.com/446391
- Remove warnings about code using deprecated declarations such as:
plat/mediatek/mt8173/bl31_plat_setup.c: In function 'bl31_platform_setup':
plat/mediatek/mt8173/bl31_plat_setup.c:175:2: warning:
'arm_gic_setup' is deprecated [-Wdeprecated-declarations]
include/drivers/arm/arm_gic.h:44:6: note: declared here:
void arm_gic_setup(void) __deprecated;
- Disable pedantic warnings to get rid of these warnings:
In file included from plat/mediatek/mt8173/bl31_plat_setup.c:36:0:
plat/mediatek/mt8173/include/mcucfg.h:134:21: error:
enumerator value for 'MP1_CPUCFG_64BIT' is not an integer constant
expression [-Werror=pedantic]
MP1_CPUCFG_64BIT = 0xf << MP1_CPUCFG_64BIT_SHIFT
BUG=none
BRANCH=none
TEST=none
Change-Id: Ifb355b8d849d119692e0dd3ca11276ddce514089
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 80c314d64a
Original-Change-Id: Ibf2c4972232b2ad743ba689825cfe8440d63e828
Original-Signed-off-by: Martin Roth <martinroth@google.com>
Original-Reviewed-on: https://review.coreboot.org/17995
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Jonathan Neuschfer <j.neuschaefer@gmx.net>
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://chromium-review.googlesource.com/446390
This fixes warnings that the new toolchain generates.
BUG=none
BRANCH=none
TEST=none
Change-Id: Ie91f31785d2f3a78b96147b4f5a41e16b8d1142f
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: a6b1b258d2
Original-Change-Id: I83d2c4c4651a89b443121312a5f36adfc1e4bc48
Original-Signed-off-by: Jonathan Neuschfer <j.neuschaefer@gmx.net>
Original-Reviewed-on: https://review.coreboot.org/18308
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://chromium-review.googlesource.com/446389
Follow up to https://review.coreboot.org/#/c/18460/
BUG=none
BRANCH=none
TEST=none
Change-Id: I829c8546ac8d9883d973ff860986389d67b620c6
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 96af0afcd7
Original-Change-Id: Ic3aada2acf3051622698e10d2e764050e16480d5
Original-Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/18475
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://chromium-review.googlesource.com/446387
This patch adds the DPTF settings specfic to the mainboard and enables
the CPU and other thermal sensors as participant device for poppy.
It enables the DPTF flag in the device tree for poppy. It also includes
the DPTF specific ASL file in the main DSDT definition.
BUG=None
BRANCH=None
TEST=Built for poppy.
Change-Id: I840b6d9fa170718b309c6a57c8d88e272bf92df5
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: d56fae18dc
Original-Change-Id: If44b01dd3c17fea06681ccf50e8e9f406e642e36
Original-Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com>
Original-Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Original-Reviewed-on: https://review.coreboot.org/17926
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/446386
Tested-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Once the PCI command register is written the bridge forwards
future IO and memory regions, as programmed in the respective base
and limit registers, to the secondary PCI bus.
It was previously argumented this is copy-paste and never known
to be required for these more recent platforms:
https://review.coreboot.org/#/c/2706/
BUG=none
BRANCH=none
TEST=none
Change-Id: If3fb9ee922b6f202a5a9d5e654066b50507b0f01
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 57d4c30e22
Original-Change-Id: Ic8911500a30bc83587af8d4b393b66783fa52e18
Original-Signed-off-by: Kysti Mlkki <kyosti.malkki@gmail.com>
Original-Reviewed-on: https://review.coreboot.org/18330
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/446385
minnow3 doesn't build right now due to API divergence on master branch.
Follow up with recent changes.
BUG=none
BRANCH=none
TEST=none
Change-Id: Ib193ed00b806294dc9210b566d7617aab6861190
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: a5c029f235
Original-Change-Id: Iee84750292f22aa040127bcbfe523a0b9eaa8176
Original-Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/18476
Original-Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Original-Tested-by: build bot (Jenkins)
Reviewed-on: https://chromium-review.googlesource.com/446384
Camera and Imaging device should be enabled for camera usecase,
FSP provides a UPD to enable/disable the SA IMGU (Imaging Unit)
expose the same as a config option in devicetree.cb
Also remove a redundant assignment for PchCio2Enable.
BUG=None
BRANCH=None
TEST=lspci should list 00:05:00
Change-Id: I8c1a35d1744079be768a985da0a7e8a54b9a268d
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: c2c8a743d1
Original-Change-Id: I4cf7daf41bfaf4dcba414921cac2e7e12bf89f37
Original-Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Original-Reviewed-on: https://review.coreboot.org/18365
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://chromium-review.googlesource.com/446760
This enables some required Kconfig options when CONFIG_CHROMEOS is set.
BUG=none
BRANCH=none
TEST=none
Change-Id: Ib21f0b166ed9aac555e3b2a9418bf4d8a07e4b74
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 30d4604e5a
Original-Change-Id: I290902746c1ea19c8bcb69540e34fde09abb9adf
Original-Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
Original-Reviewed-on: https://review.coreboot.org/18448
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/446759
This adds an oak libpayload config, that should fit all oak-based
devices such as elm.
BUG=none
BRANCH=none
TEST=none
Change-Id: Id2fa6e80e6b7fd330a9e54adb639f437a9b1424d
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 7a543d2ab9
Original-Change-Id: Iabb71404ff84029a5976371a353e8c92e781ca1f
Original-Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
Original-Reviewed-on: https://review.coreboot.org/18447
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/446758
These parameters are probably the result of copying from the Thinkpad
X60 code.
BUG=none
BRANCH=none
TEST=none
Change-Id: I91aec0b2ccdafc1134183ad897c3123b2095fcdd
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 00954f0815
Original-Change-Id: I29763b38618d4b306c37424c5c4b57dfcf69424b
Original-Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Original-Reviewed-on: https://review.coreboot.org/18290
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://chromium-review.googlesource.com/446757
Set the proper memory configuration for the MinnowBoard 3. The current
values are copied from intel/leafhill. Set the proper values for
MinnowBoard 3.
BUG=none
BRANCH=none
TEST=none
Change-Id: I422eda191c564e04331665413074b016175153ed
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 97f542efc2
Original-Change-Id: Ie37842f5ce2cabaa892f42ee945c91fe3ace527a
Original-Signed-off-by: Brenton Dong <brenton.m.dong@intel.com>
Original-Reviewed-on: https://review.coreboot.org/18374
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Original-Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://chromium-review.googlesource.com/445835
This commit adds the initial scaffolding for the MinnowBoard 3
with Apollo Lake silicon.
This mainboard is based on Intel's Leafhill CRB with Apollo Lake
silicon. In a first step, it concerns only a copy of intel/leafhill
directory with name changes. Special adaptations for MinnowBoard 3
mainboard will follow in separate commits.
BUG=none
BRANCH=none
TEST=none
Change-Id: I266e9f12db1c4824545871e6a0d1ac89f8d8255f
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 35f03d9027
Original-Change-Id: I7563fe37c89511c7035c5bffc9b034b379cfcaf4
Original-Signed-off-by: Brenton Dong <brenton.m.dong@intel.com>
Original-Reviewed-on: https://review.coreboot.org/18298
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://chromium-review.googlesource.com/445834
This file reportedly didn't compile on SUSE Linux with gcc 4.3.4:
[...]
> HOSTCC cbfstool/fsp_relocate.o
> In file included from coreboot/src/commonlib/fsp_relocate.c:18:
> coreboot/src/commonlib/include/commonlib/fsp.h:26: error:
> expected '=', ',', ';', 'asm' or '__attribute__' before
> 'fsp_component_relocate'
[...]
According to POSIX-2008[1], sys/types.h defines ssize_t, so include it.
This should not break coreboot code (as opposed to utils code), as we
have a sys/types.h in src/include.
[1]: http://pubs.opengroup.org/onlinepubs/9699919799/basedefs/sys_types.h.html
BUG=none
BRANCH=none
TEST=none
Change-Id: I61d49c1e118c7d16d2f4ec1b600796c7b996c6f3
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: b89b2c50c5
Original-Change-Id: Id3694dc76c41d800ba09183e4b039b0719ac3d93
Original-Signed-off-by: Jonathan Neuschfer <j.neuschaefer@gmx.net>
Original-Reviewed-on: https://review.coreboot.org/18417
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Nico Huber <nico.h@gmx.de>
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://chromium-review.googlesource.com/445833
This is more consistent with newer Intel targets.
BUG=none
BRANCH=none
TEST=none
Change-Id: If00a2a24cb0d9f85913fb60ef87048a2feac844c
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: b29e0b70f8
Original-Change-Id: I52ee8d3f0c330a03bd6c18eed08e578dd6ae284b
Original-Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Original-Reviewed-on: https://review.coreboot.org/18371
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://chromium-review.googlesource.com/445832
There was a 'typo' where the subsystem id was set instead of the codec
vendor id. This caused the lynxpoint HDA codecs init to fail to find
the proper codecid verbs so codecs were never initialized. That caused
the headphones jack to not work.
BUG=none
BRANCH=none
TEST=none
Change-Id: I6821c13910c1cd8c91ae6a70e15a222372b135dd
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 02756b8ffb
Original-Change-Id: I975031643fc42937ecaea2300639b90632543f67
Original-Signed-off-by: Youness Alaoui <youness.alaoui@puri.sm>
Original-Reviewed-on: https://review.coreboot.org/18411
Original-Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Original-Tested-by: build bot (Jenkins)
Reviewed-on: https://chromium-review.googlesource.com/445829
