Commit graph

1060 commits

Author SHA1 Message Date
Ronald G. Minnich
3490a5dd27 smm support from v2
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>


git-svn-id: svn://coreboot.org/repository/coreboot-v3@1060 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-11-26 18:25:42 +00:00
Stefan Reinauer
8e7ca90b6f back out until this issue is really fixed.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://coreboot.org/repository/coreboot-v3@1059 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-11-26 09:17:29 +00:00
Carl-Daniel Hailfinger
645bd273e1 Experimental backout of the critical code parts in r1057 as requested
by Stefan.
The only changes left from r1057 are:
- Added comments
- Two initial pushes of 0x00000000 (32 bits each) to the stack as safety

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>


git-svn-id: svn://coreboot.org/repository/coreboot-v3@1058 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-11-26 02:16:37 +00:00
Carl-Daniel Hailfinger
5a6f83c735 The Core2Duo CAR code did set up the stack incorrectly. In combination
with a wrong calling convention of stage1_phase1() this caused stage1 to
assume BIST had failed.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>


git-svn-id: svn://coreboot.org/repository/coreboot-v3@1057 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-11-25 23:39:31 +00:00
Stefan Reinauer
675731bf42 hack to make v3 rom access a lot faster.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://coreboot.org/repository/coreboot-v3@1056 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-11-25 23:10:24 +00:00
Stefan Reinauer
20e53b2345 get into ram init on kontron board.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://coreboot.org/repository/coreboot-v3@1055 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-11-25 22:51:15 +00:00
Stefan Reinauer
0a6c147e8e get some serial output and post codes from the dongle (trivial changes)
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://coreboot.org/repository/coreboot-v3@1054 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-11-25 22:39:00 +00:00
Ronald G. Minnich
aa662a85ad testing
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>


git-svn-id: svn://coreboot.org/repository/coreboot-v3@1053 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-11-25 20:45:32 +00:00
Ronald G. Minnich
ef9da5662d For stefan
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>


git-svn-id: svn://coreboot.org/repository/coreboot-v3@1052 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-11-25 20:18:27 +00:00
Ronald G. Minnich
d208375d81 This board now builds.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>



git-svn-id: svn://coreboot.org/repository/coreboot-v3@1051 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-11-24 22:20:48 +00:00
Ronald G. Minnich
b315b752da Simple typos and fixups. This is almost building.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>



git-svn-id: svn://coreboot.org/repository/coreboot-v3@1050 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-11-24 21:15:19 +00:00
Ronald G. Minnich
52ab2c2737 Index: northbridge/intel/i945/stage1.c
Make statics non-static (we don't do buildrom any more)
Index: northbridge/intel/i945/raminit.c
remove snarf-o that left k8 in (I used wrong script I guess?)

Index: southbridge/intel/i82801gx/libsmbus.c
Corrections (minor)

Index: southbridge/intel/i82801gx/stage1_smbus.c
static to global

Index: mainboard/kontron/986lcd-m/stage1_debug.c
don't include statictree.c

Index: mainboard/kontron/986lcd-m/stage1.c
Remove functions that have to be in initram. 

Index: mainboard/kontron/986lcd-m/initram.c
Add functions. This is all about splitting auto.c into stage1 and initram. 
stage1 is very small and limited. 

Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://coreboot.org/repository/coreboot-v3@1049 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-11-24 17:28:26 +00:00
Myles Watson
72c2e85313 This patch changes all occurrences of pci_dev_set_resources ->
pci_set_resources.  There is no matching pci_bus_set_resources, so it's
confusing to see the dev function in the bus structures.
 
Signed-off-by: Myles Watson <mylesgw@gmail.com>

Acked-by: Peter Stuge <peter@stuge.se>

git-svn-id: svn://coreboot.org/repository/coreboot-v3@1048 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-11-24 14:06:10 +00:00
Mart Raudsepp
69d6613be1 Be silent in ram_check in non-debug loglevels
As DBE61 support now runs ram_check for non-debug purposes and has expected failures
on DBE61A, downgrade the per-address looped fail notification printk and other messages
from BIOS_ERR to BIOS_DEBUG.
Document that if something is wanted to be reported in non-debug loglevels, one should
do so in the caller based on the return value.
Tweak a debug string in ram_verify to be more descriptive.

Signed-off-by: Mart Raudsepp <mart.raudsepp@artecdesign.ee>
Acked-by: Peter Stuge <peter@stuge.se>

git-svn-id: svn://coreboot.org/repository/coreboot-v3@1047 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-11-20 12:20:35 +00:00
Myles Watson
bfa2dc9335 This patch fixes the 8132 so that it can use a 40-bit address space and so
that it uses the correct functions.  Using the device functions on the bridge
was not so good for it.

Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>

git-svn-id: svn://coreboot.org/repository/coreboot-v3@1046 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-11-19 03:11:52 +00:00
Myles Watson
12a3094274 This patch makes subsystem ids work. Here are the changes by file:
device/pci_device.c:
    Only update IDs if:
    - The device is on the mainboard
    - The device has a Vendor ID and Device ID
    - The device has a set_subsystem function in ops_pci(dev)

util/dtc/flattree.c:
    Make devices from the dts be on_mainboard.
    If they're plugged in, they shouldn't be in the dts.

mainboard/amd/serengeti/dts:
    Add subsystem_vendor and subsystem_device.

Build tested on Serengeti.  Getting closer :)

Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>


git-svn-id: svn://coreboot.org/repository/coreboot-v3@1045 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-11-19 03:05:33 +00:00
Uwe Hermann
09f70836fd This is the first part of a v3 Super I/O refactoring.
Add a small collection of PNP enter/exit functions for many Super I/Os.
Use these functions instead of duplicating them for each chip.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Myles Watson <mylesgw@gmail.com>



git-svn-id: svn://coreboot.org/repository/coreboot-v3@1044 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-11-18 22:32:05 +00:00
Myles Watson
47398cfab7 This patch makes northbridge/amd/k8/pci.c use pci functions.
Build tested on Serengeti.

Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Marc Jones <marcj303@gmail.com>


git-svn-id: svn://coreboot.org/repository/coreboot-v3@1043 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-11-18 19:22:52 +00:00
Myles Watson
f75b0fe103 This patch fixes white space in northbridge/amd/pci with the help of indent.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Myles Watson <mylesgw@gmail.com>


git-svn-id: svn://coreboot.org/repository/coreboot-v3@1042 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-11-18 16:59:09 +00:00
Myles Watson
4e9c6f3669 Correct ops pointers in amd8111 dts.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>


git-svn-id: svn://coreboot.org/repository/coreboot-v3@1041 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-11-17 22:24:11 +00:00
Uwe Hermann
e5fa03aa74 Fix/finish the Winbond W83627THF/THG dts.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Myles Watson <mylesgw@gmail.com>



git-svn-id: svn://coreboot.org/repository/coreboot-v3@1040 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-11-17 20:40:39 +00:00
Myles Watson
d1eeba86f0 This patch clarifies/fixes some debug output.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Myles Watson <mylesgw@gmail.com>


git-svn-id: svn://coreboot.org/repository/coreboot-v3@1039 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-11-17 19:18:36 +00:00
Myles Watson
6e882880f2 This patch fixes debug printing.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Myles Watson <mylesgw@gmail.com>

Thanks,
Myles


git-svn-id: svn://coreboot.org/repository/coreboot-v3@1038 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-11-17 17:53:14 +00:00
Mart Raudsepp
89d507d73b artecgroup/dbe62: Remove old memory setup related commented out calls and touch up a comment.
I see no reason to have these memory work related debug calls commented out in the code, everyone should know what to locally temporarily add to debug this.

Signed-off-by: Mart Raudsepp <mart.raudsepp@artecdesign.ee>
Acked-by: Peter Stuge <peter@stuge.se>

git-svn-id: svn://coreboot.org/repository/coreboot-v3@1037 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-11-17 10:31:40 +00:00
Carl-Daniel Hailfinger
0153293887 Not a single file is being rebuilt in v3 if build.h changes. That means
the console banner and the option table will never be updated with more
recent build.h strings.

Thanks to Mart Raudsepp for spotting this oddness.

x86emu doesn't care about the contents of build.h, it just uses build.h
to check whether it is compiled in conjunction with coreboot.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Stefan Reinauer <stepan@coresystems.de>


git-svn-id: svn://coreboot.org/repository/coreboot-v3@1036 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-11-16 22:59:52 +00:00
Carl-Daniel Hailfinger
9e652d9b1f Gigabyte M57SLI compilation is broken in v3. With a small makefile and
dts change, the target compiles again.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://coreboot.org/repository/coreboot-v3@1035 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-11-16 16:09:09 +00:00
Uwe Hermann
6b0bd8acb7 Fix some incorrect entries in superio/winbond/w83627hf/dts.
The hardware monitor defaults as per datasheet are 0x0000 / 0, but on
hardware that uses this functionality it seems to be 0x290 / 5 often,
thus use those values in the dts.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Myles Watson <mylesgw@gmail.com>



git-svn-id: svn://coreboot.org/repository/coreboot-v3@1034 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-11-16 13:45:53 +00:00
Uwe Hermann
c29c991df8 Fix the incorrect VIA VT1211 LDNs, add a comment for each of them.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>



git-svn-id: svn://coreboot.org/repository/coreboot-v3@1033 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-11-16 13:41:15 +00:00
Carl-Daniel Hailfinger
0df280f294 Drop duplicated functions from W83627THG SuperI/O stage1 code and fix
up a function prototype.

Fix up #include statements for W83627THG SuperI/O stage2 code.
Use anonymous instead of named unions in struct device.
Point pnp_dev_info members to w83627thg_ops.     
Disable UART and keyboard initialization for now.
Add new code in phase3_chip_setup_dev to fill in configuration values
from the dts (code is partially disabled).

Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>


git-svn-id: svn://coreboot.org/repository/coreboot-v3@1032 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-11-16 01:52:08 +00:00
Carl-Daniel Hailfinger
3e6f0c2245 Move v2 printk_foo(...) syntax to v3 printk(BIOS_FOO, ...) syntax.
Parts of this patch (southbridge/intel/i82801gx/smi.c) were
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
The rest is
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>


git-svn-id: svn://coreboot.org/repository/coreboot-v3@1031 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-11-16 01:22:18 +00:00
Uwe Hermann
7c960311f9 Drop non-working, copy-paste superio.c file (trivial).
The build system isn't even using it so far, but if it would the
build would break (and the code wouldn't work for this hardware).

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://coreboot.org/repository/coreboot-v3@1030 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-11-15 16:17:12 +00:00
Uwe Hermann
39d6231572 Fix EPIA-CN build in v3 by dropping duplicated stop_ap() definition (trivial).
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://coreboot.org/repository/coreboot-v3@1029 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-11-15 16:13:12 +00:00
Myles Watson
18d7d33669 This patch updates the other supported SuperIOs to use the PNP dts changes.
It shouldn't break anything that was working, but I didn't try to fix SuperIOs
that weren't compiling when I started.

Compile tested on 
1. amd/dbm690t for ite/it8712f
2. amp/tinygx for ite/it8716f

I'd already updated fintek/f71805 before I realized jetway doesn't compile.

Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>


git-svn-id: svn://coreboot.org/repository/coreboot-v3@1028 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-11-14 23:03:54 +00:00
Myles Watson
27fbb8428c This patch changes PNP support for devices so that the dts values get passed
in.

include/device/pnp.h:
	Add enable, val, and irq & drq structs.

superio/winbond/w83627hf/superio.c:
	Change functions to operate on children.
	Add device ID to ops.
	Add enables to pnp_dev_info table.
	Fill in dts values.

superio/winbond/w83627hf/dts:
	Get rid of device number parameters.
	Add config parameters so we know when they're set.

device/pnp_device.c:
	Allocate devices as children to SuperIO.

mainboard/amd/serengeti/dts:
	Move ioport so it's found. (Not its permanent resting place I hope.)
	Add enables for KBC, SP1, and HWM to show it off.

Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>


git-svn-id: svn://coreboot.org/repository/coreboot-v3@1027 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-11-14 21:45:10 +00:00
Ronald G. Minnich
863bcbff3b Two remaining issues:
/home/rminnich/coreboot-v3/build/coreboot.initram_partiallylinked.o: section .data.rel.ro.local: dual_channel_slew_group_lookup.3242 single_channel_slew_group_lookup.3243

and
/home/rminnich/coreboot-v3/southbridge/intel/i82801gx/smbus.c:34: error: conflicting types for ‘smbus_read_byte’
include/device/smbus.h:56: error: previous declaration of ‘smbus_read_byte’ was here

we are working these. The second is much harder than it seems. 
It concerns whether we put i2c devices (i.e. DRAM spd SEEPROMS) in the dts.

Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>


git-svn-id: svn://coreboot.org/repository/coreboot-v3@1026 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-11-14 17:14:16 +00:00
Ronald G. Minnich
dd5e033e5f Get rid of un-needed functions in initram.c
Comment out not-yet-supplied initialize_cpus.

Fix missing ; in smbus.c

Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>


git-svn-id: svn://coreboot.org/repository/coreboot-v3@1025 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-11-14 16:21:21 +00:00
Myles Watson
981c3652a1 This patch adds some debug functions, cleans up whitespace (per indent), and adds const in a few places.
include/device/path.h
	Make path_eq take const path*.
	
include/device/device.h
	Use const with dev_path, dev_id_string, bus_path, find_dev_path,
	andalloc_find.

device/device.c
	Add functions for tree printing of devs and resources.
	Change %p to more useful info.

device/device_util.c
	Use const changes from device.h.

lib/stage2.c
	Use updated printing functions.

Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>


git-svn-id: svn://coreboot.org/repository/coreboot-v3@1024 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-11-14 16:15:33 +00:00
Ronald G. Minnich
f222dfc6f5 These are all cleanups to get it closer to building.
Lots more to do. 

Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>


git-svn-id: svn://coreboot.org/repository/coreboot-v3@1023 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-11-14 15:58:59 +00:00
Mart Raudsepp
02e9024faf artecgroup/dbe61: Use existing struct definition from arch/x86/msr.h instead of our own
Signed-off-by: Mart Raudsepp <mart.raudsepp@artecdesign.ee>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>

git-svn-id: svn://coreboot.org/repository/coreboot-v3@1022 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-11-14 15:25:22 +00:00
Myles Watson
b875333abf This patch makes it so serengeti builds again.
It includes an ide option that has to be there, and fixes a CPU test in
Kconfig.

Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Myles Watson <mylesgw@gmail.com>


git-svn-id: svn://coreboot.org/repository/coreboot-v3@1021 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-11-14 15:19:39 +00:00
Ronald G. Minnich
f24d97a791 Index: northbridge/intel/i945/stage1.c
Make statics non-static (we don't do buildrom any more)

Index: northbridge/intel/i945/raminit.c
remove snarf-o that left k8 in (I used wrong script I guess?)

Index: southbridge/intel/i82801gx/stage1_smbus.c
static to global

Index: mainboard/kontron/986lcd-m/stage1.c
Remove functions that have to be in initram. 

Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://coreboot.org/repository/coreboot-v3@1020 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-11-14 14:49:28 +00:00
Ronald G. Minnich
5a205b9067 Add core2 stage1.c dependency
Index: arch/x86/intel/core2/stage1.c
Initial core2 disable_car and stop_ap
disable_car is wrong but we can fix that tomorrow -- it's core 2 day on friday!

Index: arch/x86/via/stage1.c
Add empty stop_ap()

Index: mainboard/kontron/986lcd-m/stage1_debug.c
Cleanup
Index: mainboard/kontron/986lcd-m/initram.c
Cleanup
Index: mainboard/jetway/j7f2/stage1.c
Remove definition of stop_ap; this belongs in the cpu!
Index: southbridge/intel/i82801gx/libsmbus.c
Fix definition of TIMEOUT (i.e. remove it)

Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>


git-svn-id: svn://coreboot.org/repository/coreboot-v3@1019 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-11-14 05:05:24 +00:00
Mart Raudsepp
321ff1c2f6 artecgroup/dbe61: Get DBE61A RAM setup and timing working.
* Uncomment the dbe61a SPD table
* Modify spd_read_byte to support a DIMM SPD address at DIMM_DBE61A that outputs data from dbe61a SPD table instead of dbe61c; approach tip from Marc Jones
* In main() after setting up DBE61C 256MB RAM, run a ram_check, and if that returns a greater than zero verify error count set up 128MB for DBE61A instead
* Tweak the dbe61a SPD table to result in LX MSR values as known to work in Artec v2 branch - this is DBE62/DBE61C values, with density and NUM_COLUMNS halved, and some timings tweaked according to the v2 results.

Now memtest86+ is quite happy on both DBE61C and DBE61A.

Note that it should be better to ram_check in the high memory areas, but that doesn't seem to currently work.
Low memory check seems fine for the immediate time being, as the results appear shifted there as well with the wrong size/timing setup.

Signed-off-by: Mart Raudsepp <mart.raudsepp@artecdesign.ee>

Good enough for now.
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>

git-svn-id: svn://coreboot.org/repository/coreboot-v3@1018 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-11-13 17:55:39 +00:00
Ronald G. Minnich
de750a1e1c fix compile errors and Ron's Makefile mistake.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>


git-svn-id: svn://coreboot.org/repository/coreboot-v3@1017 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-11-13 17:42:52 +00:00
Mart Raudsepp
7e53fa9101 artecgroup/dbe61: Gather RAM initialization function calls to one helper function.
Then we can later use it for re-initializing for different SPD without code duplication.

Signed-off-by: Mart Raudsepp <mart.raudsepp@artecdesign.ee>
Acked-by: Peter Stuge <peter@stuge.se>

git-svn-id: svn://coreboot.org/repository/coreboot-v3@1016 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-11-13 17:14:16 +00:00
Mart Raudsepp
72f38d1a3d artecgroup/dbe61: Use dbe61c specific variables and macros instead of generic ones
This is in preparation of dbe61a handling addition.

Uses DIMM_DBE61C and DIMM_EMPTY instead of generic DIMM0/DIMM1, and
spd_table_dbe61c instead of spd_table.

Also removes a completely unused smb_devices structure definition.

Signed-off-by: Mart Raudsepp <mart.raudsepp@artecdesign.ee>
Acked-by: Peter Stuge <peter@stuge.se>

git-svn-id: svn://coreboot.org/repository/coreboot-v3@1015 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-11-13 17:12:34 +00:00
Mart Raudsepp
6cc92990ce Return the count of failures from ram_check.
Will be necessary for DBE61 automatic memory size selection.

Signed-off-by: Mart Raudsepp <mart.raudsepp@artecdesign.ee>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>

git-svn-id: svn://coreboot.org/repository/coreboot-v3@1014 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-11-13 17:04:11 +00:00
Carl-Daniel Hailfinger
99e68b9345 Kill v2 leftovers.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>


git-svn-id: svn://coreboot.org/repository/coreboot-v3@1013 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-11-13 01:53:55 +00:00
Carl-Daniel Hailfinger
cb9db3b6d0 We are woefully unaware about how much stack v3 really uses.
This is a complete rewrite of my earlier stack checker proposal.
It works for CAR and RAM, has better abstraction and actually gives us
nice results.
The stack checker is default off due to its rather measurable impact on
boot speed.
Diagnostic messages are printed on first initialization, directly after
RAM init and directly before passing control to the payload. Sample qemu
log is attached. Extract from that log follows:

coreboot-3.0.986 Fri Nov  7 04:04:37 CET 2008 starting...
(console_loglevel=8)
Initial lowest stack is 0x0008fe98
Choosing fallback boot.
[...]
Done RAM init code
After RAM init, lowest stack is 0x0008fe30
Done printk() buffer move
[...]
LAR: load_file_segments: Failed for normal/payload
Before handoff to payload, lowest stack is 0x0008bf50
FATAL: No usable payload found.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://coreboot.org/repository/coreboot-v3@1012 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-11-13 01:28:32 +00:00
Peter Stuge
35b5759efb Remove insignificant unused spd_devices arrays.
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>


git-svn-id: svn://coreboot.org/repository/coreboot-v3@1011 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-11-13 01:04:35 +00:00