cbgfx currently does not support portrait screen which height >width.
so add it.
BUG=none
BRANCH=none
TEST=none
Change-Id: I5efd25158e383f675131e0c6469b7af5147f908e
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: d0e465456e
Original-Change-Id: I66fee6d73654e736a2db4a3d191f030c52a23e0d
Original-Signed-off-by: Nickey Yang <nickey.yang@rock-chips.com>
Original-Reviewed-on: https://review.coreboot.org/19474
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/494047
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
input_underrun is defined but not used. A reasonably new compiler,
enabled warnings and warnings-as-error make the build break for no good
reason.
BUG=none
BRANCH=none
TEST=none
Change-Id: I9b3f117ef563d8828b09f5c09e91874925b685d0
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: c854e943e0
Original-Change-Id: Ibeb7ba53aad5738938093ab7b34695c9c99c9afe
Original-Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/19482
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
Reviewed-on: https://chromium-review.googlesource.com/493971
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
This patch allows the CBMEM console to persist across reboots, which
should greatly help post factum debugging of issues involving multiple
reboots. In order to prevent the console from filling up, it will
instead operate as a ring buffer that continues to evict the oldest
lines once full. (This means that if even a single boot doesn't fit into
the buffer, we will now drop the oldest lines whereas previous code
would've dropped the newest lines instead.)
The console control structure is modified in a sorta
backwards-compatible way, so that new readers can continue to work with
old console buffers and vice versa. When an old reader reads a new
buffer that has already once overflowed (i.e. is operating in true ring
buffer mode) it will print lines out of order, but it will at least
still print out the whole console content and not do any illegal memory
accesses (assuming it correctly implemented cursor overflow as it was
already possible before this patch).
BUG=chromium:651966
TEST=Rebooted and confirmed output repeatedly on a Kevin and a Falco.
Also confirmed correct behavior across suspend/resume for the latter.
Change-Id: I927df6bbffa13fdce9d1984278afa340042f7ac9
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: d67c6876b5
Original-Change-Id: Ifcbf59d58e1ad20995b98d111c4647281fbb45ff
Original-Signed-off-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/18301
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/482975
When console input driver registers itself, perform flush of input
buffer to avoid interpreting any stale key presses before libpayload
is run.
keyboard.c: Remove the redundant buffer flush.
8250.c: Ensure that serial_hardware_is_present is set before call to
add input driver.
BUG=b:37273808
TEST=Verified that any key presses in serial console before payload is
up do not have any effect after the payload starts running.
Change-Id: I473423c4d5f701dbe16e490c49e910816c9af6a0
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 342f5f836c
Original-Change-Id: I46f1b6715ccf6418f5b2c741bf90db2ece26a60d
Original-Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/19345
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/482972
SeaBIOS 1.10.2 was released on February 28th, 2017 [1][2] with the
changes below.
```
$ git log --oneline rel-1.10.1..rel-1.10.2
5f4c7b1 QEMU fw_cfg: Write fw_cfg back on S3 resume
c45ca70 QEMU fw_cfg: Add functions for accessing files by key
31b6229 QEMU fw_cfg: Add command to write back address of file
aa7219d romfile-loader: Switch to using named structs
2a1d88c QEMU DMA: Add DMA write capability
d2ac564 ps2port: Disable keyboard/mouse prior to resetting ps2 controller
b0e3c67 vgasrc: Increase debug level
ca3ab93 ahci: Set upper 32-bit registers to zero
```
This fixes the problem on a Lenovo X60, that the keyboard is not
initialized by SeaBIOS when for example loaded from GRUB.
[1] https://www.seabios.org/Releases#SeaBIOS_1.10.2
BUG=none
BRANCH=none
TEST=none
Change-Id: I5c211ab028c2f93e46fd6f033c8a4abfd0954623
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 1560fbf6d6
Original-Change-Id: Idc078ffa896b2e105faabd2d8befeaf9a2a0b6ac
Original-Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Reviewed-on: https://review.coreboot.org/19290
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://chromium-review.googlesource.com/480292
Update from commit 124af94f - Fri Feb 26, 2016
(skylake boards: unconditionally re-enable 8254 PIT for legacy)
To commit eb583fa8 - Wed Mar 29, 2017
(rk3399_sdhci: Reintroduce PHY power-cycling at 52MHz)
This brings the stable version of depthcharge forward by 325 commits.
BUG=none
BRANCH=none
TEST=none
Change-Id: I47dcabd8e8ca63d6fba94f93bfeae93d1bde722a
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 973104ba1f
Original-Change-Id: I31b3235df6d36409ff1b365e6adb6852281df097
Original-Signed-off-by: Martin Roth <martinroth@google.com>
Original-Reviewed-on: https://review.coreboot.org/19220
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://chromium-review.googlesource.com/480106
Update from commit 2afd66eb - Fri Jul 29, 2016
([pixbuf] Enable PNG format by default)
To commit fd6d1f46 - Fri Mar 31, 2017
([thunderx] Use ThunderxConfigProtocol to obtain board configuration)
This moves the stable iPXE commit forward 144 commits.
BUG=none
BRANCH=none
TEST=none
Change-Id: I6d4fd8e38d5adfcd4223c14f666d8963af21a7cc
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 1a693958eb
Original-Change-Id: Ia0c97f863be39632c9206ca95b3857047fc37e26
Original-Signed-off-by: Martin Roth <martinroth@google.com>
Original-Reviewed-on: https://review.coreboot.org/19221
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Philippe Mathieu-Daud <philippe.mathieu.daude@gmail.com>
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Reviewed-by: Timothy Pearson <tpearson@raptorengineering.com>
Original-Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://chromium-review.googlesource.com/480105
CBGFX currently doesn't support portrait screens at all. This will have
to be fixed eventually but might take a bit of effort. As a first step
to make devices with a portrait panel somewhat usable, this patch will
just force a square canvas on these panels and keep the bottom part of
the screen black.
Also switch set_pixel to calculate framebuffer position via
bytes_per_line instead of x_resolution. This is supposed to be the
canonical way to do that and may differ in cases where the display
controller requires a certain alignment from framebuffer lines.
BRANCH=none
BUG=b:35774871
TEST=Boot Rowan in developer mode and see output on the
panel; below the developer screen square is completely black
Change-Id: I5e5423e5fe166b1fea54ab16f7e0dd31fcce00d7
Original-Change-Id: I47dd3bf95ab8a7d8b7e1913e0ddab346eedd46f1
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/479613
Commit-Ready: Daniel Kurtz <djkurtz@chromium.org>
Tested-by: Daniel Kurtz <djkurtz@chromium.org>
This adds a gru libpayload config, that should fit all gru-based
devices such as kevin.
As gru-based devices are CrOS devices, select the associated config
to enable CrOS-specific features.
BUG=none
BRANCH=none
TEST=none
Change-Id: I4e7112bb82e790719bc608ce8fe2f852f56e3ce2
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 038818f00c
Original-Change-Id: I6e79b763fc497c126612b8786a669a33b57ea29f
Original-Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
Original-Reviewed-on: https://review.coreboot.org/19137
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/472710
Enable the USB during the initialization of tint. Without it USB
keyboards don't work, which makes this payload pointless on
systems where a PS/2 keyboard port isn't available.
Based on I98f0ccdb19d6b195572941cf87ce3221f57db7c5 (tint and
nvramcui: enable USB, update tint to 0.04+nmu1 with changes) [1]
[1] https://review.coreboot.org/17507/
BUG=none
BRANCH=none
TEST=none
Change-Id: Ie04af809b6f6c6f97554eced7d8477d052ec6f60
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 85e81dfa6d
Original-Change-Id: Iaa8dfac0301ef19a2d76a0975d025b00e7f3807b
Original-Signed-off-by: Nicola Corna <nicola@corna.info>
Original-Reviewed-on: https://review.coreboot.org/18766
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://chromium-review.googlesource.com/457364
We have found a non-compliant USB hub (RealTek RTS 5413) that does not
set a port's Connect Status Change bit on its USB 3.0 half if the port
had already been connected while the hub was being reset. To work around
this bug, this patch adds code to initially request the status of every
port after a hub was enumerated, clear the Connect Status Change bit if
set, and then enumerate the port iff it is currently connected,
regardless of whether the change bit was set. A similar behavior can
also be found in the Linux kernel.
BRANCH=oak
BUG=b:35929438
TEST=Booted Elm with this change, my USB 3.0 sticks enumerate now even
if they had been plugged in since boot.
Change-Id: If438b4acac2c509c7f22d9cc2470a014560bb00e
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 5fae829410
Original-Change-Id: I8a28252eb94f005f04866d06e4fc61ea265cee89
Original-Signed-off-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/18729
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://chromium-review.googlesource.com/455825
Enable the USB during the initialization of nvramcui. Without it
the USB keyboards don't work, which makes this payload pointless
on the systems where a PS/2 keyboard port isn't available.
Based on https://review.coreboot.org/#/c/17507/
BUG=none
BRANCH=none
TEST=none
Change-Id: I794d780072cdd36c98b2dac0012ecb69c1d609e2
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: fece39baa5
Original-Change-Id: I04697c5f582b41e6f6ffe98955bf59f4fe57f66e
Original-Signed-off-by: Nicola Corna <nicola@corna.info>
Original-Reviewed-on: https://review.coreboot.org/18765
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://chromium-review.googlesource.com/454543
Allows to use SSE and floating point in payloads without digging to
much into x86 assembly code.
Tested on Lenovo T500 (Intel Core2Duo).
Both floating point operation and SSE is properly working.
BUG=none
BRANCH=none
TEST=none
Change-Id: I5869905873f0bacfeb38d7e81d25d956a676ffb5
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: b854ae2649
Original-Change-Id: I4a5fc633f158de421b70435a8bfdc0dcaa504c72
Original-Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Original-Reviewed-on: https://review.coreboot.org/18345
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://chromium-review.googlesource.com/451619
Since version 9332965 "serialio: Support for mmap serial ports", SeaBIOS
supports memory mapped serial ports. This patch automatically configures
SeaBIOS when the Hudson UART is enabled.
BUG=none
BRANCH=none
TEST=none
Change-Id: I3a0b85f4e566c77847cc201c827a45c4f74b19e1
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 77ced402fb
Original-Change-Id: I072f6a957df7e143d790783546b0725bcd597d9c
Original-Signed-off-by: Ricardo Ribalda Delgado <ricardo.ribalda@gmail.com>
Original-Reviewed-on: https://review.coreboot.org/18025
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://chromium-review.googlesource.com/449814
This change is based on the following commit:
3aa91dc payloads/seabios: Add "git revision" to the SeaBIOS version menu
BUG=none
BRANCH=none
TEST=none
Change-Id: Iaee9f1240d01b1055b05320b2cfb2263d819f409
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 08cf195f4c
Original-Change-Id: I9987e3673e70b5cb20173d1ddff6060f42a5374a
Original-Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo@no-log.org>
Original-Reviewed-on: https://review.coreboot.org/18352
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://chromium-review.googlesource.com/446392
This adds an oak libpayload config, that should fit all oak-based
devices such as elm.
BUG=none
BRANCH=none
TEST=none
Change-Id: Id2fa6e80e6b7fd330a9e54adb639f437a9b1424d
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 7a543d2ab9
Original-Change-Id: Iabb71404ff84029a5976371a353e8c92e781ca1f
Original-Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
Original-Reviewed-on: https://review.coreboot.org/18447
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/446758
Configure GRUB to build with boot time statistics. That allows users
to add that module to GRUB by adding `boottime` to the list of extra
modules.
BUG=none
BRANCH=none
TEST=none
Change-Id: Iab5d114c243119bd539ef2aec1efacd2eacd2f58
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 7c7b176169
Original-Change-Id: I76a07e49aecb37652fe8c7d6a9421fd464424287
Original-Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Original-Reviewed-on: https://review.coreboot.org/18367
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://chromium-review.googlesource.com/445142
Some simple implementation of the MultiBoot protocol may not pass a
memory map (MULTIBOOT_FLAGS_MMAP missing in the flags) but just the two
values for low and high memory, indicated by the MULTIBOOT_FLAGS_MEMINFO
flag.
Support those kind of boot loaders too, instead of falling back to the
hard-coded values in lib_get_sysinfo().
Tested with a multiboot enhanced version of FILO.
BUG=none
BRANCH=none
TEST=none
Change-Id: I4c1d95a8f4aa8735538dad85d5f856ce36a5f72e
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 898de6111a
Original-Change-Id: I22cf9e3ec0075aff040390bd177c5cd22d439b81
Original-Signed-off-by: Mathias Krause <minipli@googlemail.com>
Original-Reviewed-on: https://review.coreboot.org/18350
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://chromium-review.googlesource.com/445141
Implement the argc/argv passing as described in coreboots payload API:
http://www.coreboot.org/Payload_API
While at it, give the code some love by not needlessly trashing register
values.
BUG=none
BRANCH=none
TEST=none
Change-Id: If49874b1ac1c7359816f4ec02c5380c32101fa1a
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Original-Commit-Id: d2f16cac74
Original-Change-Id: Ib830f2c67b631b7216843203cefd55d9bb780d83
Original-Signed-off-by: Mathias Krause <minipli@googlemail.com>
Original-Reviewed-on: https://review.coreboot.org/18336
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Tested-by: build bot (Jenkins)
Reviewed-on: https://chromium-review.googlesource.com/444817
Simplify the code by directly using the arguments on the stack as base
pointer relative memory references, instead of loading them into
intermediate registers first.
Make it more robust by preserving all callee saved registers mandated by
the C calling convention (and only those), namely EBP, EBX, ESI and EDI.
Don't assume anything about the register state when the called function
returns -- beside the segment registers and the stack pointer to be
still the same as before the call.
BUG=none
BRANCH=none
TEST=none
Change-Id: I231828bb9a65a6b1077b17024c0c59fed8546284
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Original-Commit-Id: 57dc93c967
Original-Change-Id: I383d6ccefc5b3d5cca37a1c9b638c231bbc48aa8
Original-Signed-off-by: Mathias Krause <minipli@googlemail.com>
Original-Reviewed-on: https://review.coreboot.org/18335
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Tested-by: build bot (Jenkins)
Reviewed-on: https://chromium-review.googlesource.com/444816
According to coreboots payload API [1], the called payload should be
able to return a value via %eax. Support this by changing the prototype
of start_main() and pass on the return value of main() to the caller
instead of discarding it.
[1] https://www.coreboot.org/Payload_API
BUG=none
BRANCH=none
TEST=none
Change-Id: I1782c45b615d431de8be5a533d5890ed53ddb9d8
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Original-Commit-Id: 7b681c5926
Original-Change-Id: I8442faea19cc8e04487092f8e61aa4e5cba3ba76
Original-Signed-off-by: Mathias Krause <minipli@googlemail.com>
Original-Reviewed-on: https://review.coreboot.org/18334
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/444815
According to coreboots payload API [1] the argc value should be passed
at stack offset 0x10, so we need to push a dummy value to comply to the
API.
[1] https://www.coreboot.org/Payload_API
BUG=none
BRANCH=none
TEST=none
Change-Id: I2acc66d20fcc4e313d1ddbc4a7bc1772548981c5
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Original-Commit-Id: 9fa78c136d
Original-Change-Id: Id20424185a5bf7e4d94de1886a2cece3f3968371
Original-Signed-off-by: Mathias Krause <minipli@googlemail.com>
Original-Reviewed-on: https://review.coreboot.org/18333
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/444814
The pointer to write the return value to is in %ecx, not %eax. Writing
to (%eax) leads to memory corruptions as %eax holds the return value,
e.g. would write zero to address zero for a "successful" returning
payload.
BUG=none
BRANCH=none
TEST=none
Change-Id: I92d9ceec19d236e756c4eaf2ecf9c0534a3ad482
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Original-Commit-Id: 901efea8ab
Original-Change-Id: I82df27ae89a9e3d25f479ebdda2b50ea57565459
Original-Signed-off-by: Mathias Krause <minipli@googlemail.com>
Original-Reviewed-on: https://review.coreboot.org/18332
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/443927
Change depthcharge to not require a board-specific config file for
libpayload. If the Kconfig option is selected, use the settings
in libpayload/configs/defconfig instead.
BUG=none
BRANCH=none
TEST=none
Change-Id: Iaa3f43f385dd9e90a80e760016f18eddb6a6ffd1
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: fc18507134
Original-Change-Id: I4fd1a5915472f28e757c62f3f2415716f1fdfc71
Original-Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Original-Reviewed-on: https://review.coreboot.org/18271
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://chromium-review.googlesource.com/435810
Add the capability for specifying which version of depthcharge to
checkout and build. This is similar to the existing feature for
SeaBIOS.
The depthcharge makefile already contains some structure for checking
out master vs. stable however the calling Makefile.inc ingored this
feature. Add the command-line variable assignment for these, along
with a tree-ish for any revision.
BUG=none
BRANCH=none
TEST=none
Change-Id: Ie9b7ffaf1dc5a4d3e7ffbc00794f1f1b1ccbaa0b
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: f9973b5c2b
Original-Change-Id: I99a5b088cb0ebb29e5d96a84217b3bfa852de8ac
Original-Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Original-Reviewed-on: https://review.coreboot.org/18270
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://chromium-review.googlesource.com/435809
Depending on the commit to build, depthcharge may have a different
target name (depthcharge vs. depthcharge_unified). Add some logic
to determine which name should be used based on the commit ID
being requested.
BUG=none
BRANCH=none
TEST=none
Change-Id: Ic008bb20846b55640b97140b1c08ddf7eb0f92a7
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 8f470c7a7e
Original-Change-Id: I05b853934d13696f4bd0d79d53ff6c5f59096d1c
Original-Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Original-Reviewed-on: https://review.coreboot.org/18269
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://chromium-review.googlesource.com/435808
Drop the _unified moniker from the depthcharge build. The payload
and coreboot have drifted out of sync and there is no longer a
non-unified depthcharge.
This patch corresponds with the depthcharge change:
https://review.coreboot.org/cgit/depthcharge.git/commit/?id=74a0739
BUG=none
BRANCH=none
TEST=none
Change-Id: Id6d090edec4fe1a8194bfabee5afb8b8f42f200e
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 9e33e27a46
Original-Change-Id: I8d028b14d2eee63dfdc9d3dd63695f1c58ea7984
Original-Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Original-Reviewed-on: https://review.coreboot.org/18268
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://chromium-review.googlesource.com/435807
The SeaBIOS and coreboot log levels don't really align, so setting the
SeaBIOS log level to the same as coreboot's isn't really what we want.
- Update default log level to use the default SeaBIOS log level.
- Update the current help text to match the new defaults.
- Add help text for what is displayed at various levels.
- Get rid of separate type & prompt lines.
- Add comments for default seabios level & logging disabled
BUG=none
BRANCH=none
TEST=none
Change-Id: I4ce561f8b99aa000359aa86af23506274ffb4535
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 8556db35e0
Original-Change-Id: I5a8b75bd44748cb94a83a77ac3a379c8a9587e7b
Original-Signed-off-by: Martin Roth <martinroth@google.com>
Original-Reviewed-on: https://review.coreboot.org/18210
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Nico Huber <nico.h@gmx.de>
Original-Reviewed-by: Kevin O'Connor <kevin@koconnor.net>
Reviewed-on: https://chromium-review.googlesource.com/433983
Make the code C89 compatible, which doesnt allow loop initial
declarations. Older compilers use C89 by default, so just declare the
variable outside.
BUG=none
BRANCH=none
TEST=none
Change-Id: If89c5f7ab563e8acde3150c57611a432d72509dd
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: e7385d14b1
Original-Change-Id: I3c5a8109e66f7a25687f4e4b2c72718d74276e04
Original-Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Reviewed-on: https://review.coreboot.org/18196
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://chromium-review.googlesource.com/431984
When .xcompile doesn't already exist, building libpayload fails because
the CC variable (et al) remain empty since .xcompile is only included
after the variables coming from there are evaluated.
BUG=none
BRANCH=none
TEST=none
Change-Id: Ie18787c4d871681de72e15ab6275a2f0003ed622
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: b144a34c60
Original-Change-Id: I73f1cbced95afcff15839604fea5fd05d81bc3d3
Original-Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/18228
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://chromium-review.googlesource.com/432758
It takes a long time for no gain: We don't need to update the
submodules, we don't need to fetch the revision, we don't need to find
the compilers, when all we want to do is to manipulate the .config file
or clean the build directory.
BUG=none
BRANCH=none
TEST=none
CQ-DEPEND=CL:432758
Change-Id: I2a2e65d1f5945885b43e32ecb8406f83f973c106
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 0ffef882d8
Original-Change-Id: Ie1bd446a0d49a81e3cccdb56fe2c43ffd83b6c98
Original-Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/18182
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://chromium-review.googlesource.com/431983
This enables USB HID support in the veyron config, since it seems to
work correctly and is needed for interaction with depthcharge on devices
without an embedded keyboard (such as veyron_mickey).
BUG=none
BRANCH=none
TEST=none
Change-Id: Ic1ed2987074924fdab987974ad8e5bb7c9006f15
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 3e7f14bfae
Original-Change-Id: Icae829e3a132005df17bcb6f7e6f8a190912576d
Original-Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
Original-Reviewed-on: https://review.coreboot.org/17930
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/430715
This fixes the generic timer driver to get the current tick from the
high register, so that comparison with the high count value (obtained
previously from the same register) has a chance to succeed.
BUG=none
BRANCH=none
TEST=none
Change-Id: I5ce02bfa15a91ad34641b8e24813a5b7ca790ec3
Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
Reviewed-on: https://review.coreboot.org/17929
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://chromium-review.googlesource.com/427823
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Stefan Reinauer <reinauer@chromium.org>
There was some ongoing development on the generic timer driver after it
was merged into CrOS libpayload, so fetch that.
BUG=none
BRANCH=none
TEST=none
CQ-DEPEND=CL:427823
Change-Id: I78c38eb8c8a3aca66a08e702978a7290a26fd3d7
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/427822
Reviewed-by: Stefan Reinauer <reinauer@chromium.org>
Previously SeaBIOS's default was used (1). This patch defaults to
coreboot's console level instead which is approximately the same
verbosity as SeaBIOS and thus what a user would probably expect.
BUG=none
BRANCH=none
TEST=none
Change-Id: Ic99aad03d625b6d81ce0a047c35a39074985f3d6
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: c48d791506
Original-Change-Id: If79e5f40c9380bb527f870eeb7d0cb43faf00beb
Original-Signed-off-by: Stefan Tauner <stefan.tauner@gmx.at>
Original-Reviewed-on: https://review.coreboot.org/18051
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://chromium-review.googlesource.com/430180
Reviewed-by: Stefan Reinauer <reinauer@chromium.org>
power button is usually dropped because it's not
in the keyboard matrix range. Adding in condition
to forward it like other keys.
BUG=chrome-os-partner:61275
BRANCH=None
TEST=reboot and make sure power button selection
in detachable menus is processed on reef.
Change-Id: I516a0043bd7730789728d5c5498d0a0f30a2acac
Signed-off-by: Shelley Chen <shchen@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/428199
Reviewed-by: Randall Spangler <rspangler@chromium.org>
This updates the configuration for ARM CrOS devices (nyans and veyrons)
by using the CHROMEOS Kconfig option, thus reducing the number of
options to select. It also brings proper serial console support.
BUG=none
BRANCH=none
TEST=none
Change-Id: I455b66801c3518319e078aa63d63b515ee80cd22
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 7a9ec36fd4
Original-Change-Id: Iffc84c44a1d339c5bb575fbaffc40bc2d56bb6cf
Original-Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
Original-Reviewed-on: https://review.coreboot.org/17928
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/428258
Commit-Ready: Aaron Durbin <adurbin@chromium.org>
Currently we just disabled ohci interrupts when calling ohci_shutdown,
Which would not actually shutdown the ohci controller, for example it
may still written the increased HccaFrameNumber to Hcca buffer.
Perform a soft reset to ohci controller as the linux kernel ohci-hcd
driver does.
BUG=chrome-os-partner:60996
BRANCH=None
TEST=Checked on gru, no more "BUG: Bad page state" error in kernel.
Change-Id: I3f192aea627ba2fa69533bc0a4270466ca18f2a7
Signed-off-by: Jeffy Chen <jeffy.chen@rock-chips.com>
Reviewed-on: https://chromium-review.googlesource.com/426338
Reviewed-by: Douglas Anderson <dianders@chromium.org>
BUG=chrome-os-partner:56947
TEST=Verifed country code can be parsed from VPD in depthcharge.
BRANCH=None
Change-Id: I4616fefc6a377d7830397cdadb493927358e25cc
Signed-off-by: Kan Yan <kyan@google.com>
Reviewed-on: https://chromium-review.googlesource.com/425819
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Changes since SeaBIOS 1.9.3
Release 1.10.0:
* Initial support for Trusted Platform Module (TPM) version 2.0
* Several USB XHCI timing fixes on real hardware
* Support for "LSI MPT Fusion" scsi controllers on QEMU
* Support for virtio devices mapped above 4GB
* Several bug fixes and code cleanups
Release 1.10.1:
* Updates for QEMU for reproducible builds
Change-Id: I465700307d72fa44b6900b38b332603ea505ed09
Original-Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org>
Original-Reviewed-on: https://review.coreboot.org/18026
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/425980
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Coverity considers this a copy&paste error, and maybe it is. In any
case, it makes sense to check the variable that (if the condition is
true) is changed, and the values are the same before that test, so the
change is harmless.
BUG=None
BRANCH=None
TEST=None
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Found-by: Coverity Scan #1347376
Reviewed-on: https://review.coreboot.org/17837
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Change-Id: I163c6a9f5baa05e715861dc19643b19a9c79c883
Reviewed-on: https://chromium-review.googlesource.com/420839
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Coverity erroneously complains that we call wmove with x or y == -1,
even though our copy of that function properly checks for that.
But: setsyx is documented to always return OK (even on errors), so let
it do that. (and make coverity happy in the process)
BUG=None
BRANCH=None
TEST=None
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Found-by: Coverity Scan #1260797
Reviewed-on: https://review.coreboot.org/17836
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Change-Id: I1bc9ba2a075037f0e1a855b67a93883978564887
Reviewed-on: https://chromium-review.googlesource.com/420838
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
