Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@1061 f3766cd6-281f-0410-b1cd-43a5c92072e9
Parts of this patch (southbridge/intel/i82801gx/smi.c) were
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
The rest is
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@1031 f3766cd6-281f-0410-b1cd-43a5c92072e9
This is from v2. Once again, the pattern:
- save the chip name for the common enable parts, hence i82801gx.c
- remove the leading i82801_ from most other bits, since we compile
in different directories now
- Every device of a type has a distinct .c file (e.g. pcie.c)
- Each device of a type may be realized in more than one bit of silicon,
and have more than one set of operations, although code is common.
These are placed into distinct operations structs (see pcie.c)
- for every distinct device, there is a .dts file.
This set of rules makes for simple cross-part standardization of code.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@991 f3766cd6-281f-0410-b1cd-43a5c92072e9
