Commit graph

8 commits

Author SHA1 Message Date
Myles Watson
d4480beaec specific-resources.diff:
This patch makes specific devices use the updated resource allocation code.

The changes necessary are:
	1. Remove all calls to compute_allocate_resources.
	2. Don't store resources except in phase4_set_resources.

northbridge/amd/k8/pci.c:
	Remove calls to compute_allocate_resource.
	Change phase4_assign_resources to phase4_set_resources

southbridge/amd/amd8132/amd8132_bridge.c:
	Remove NPUML and NPUMB.
	Add a warning for bus disabling.
	Remove bridge_{read|set}_resources (they were there for NPUML)
	
southbridge/nvidia/mcp55/lpc.c:
southbridge/amd/sb600/lpc.c:
	Remove references to have_resources.

southbridge/amd/amd8111/lpc.c:
	Add resources for subtractive IO and ROM.

northbridge/amd/k8/domain.c:
northbridge/intel/i440bxemulation/i440bx.c:
northbridge/amd/geodelx/geodelx.c:
northbridge/intel/i945/northbridge.c:
northbridge/via/cn700/stage2.c:
	Change phase4_assign_resources->phase4_set_resources.
	
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>



git-svn-id: svn://coreboot.org/repository/coreboot-v3@1090 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-12-31 19:46:14 +00:00
Myles Watson
72c2e85313 This patch changes all occurrences of pci_dev_set_resources ->
pci_set_resources.  There is no matching pci_bus_set_resources, so it's
confusing to see the dev function in the bus structures.
 
Signed-off-by: Myles Watson <mylesgw@gmail.com>

Acked-by: Peter Stuge <peter@stuge.se>

git-svn-id: svn://coreboot.org/repository/coreboot-v3@1048 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-11-24 14:06:10 +00:00
Marc Jones
ea883f4ad2 Whitespace cleanup on AMD southbridge device_operations structs. (trivial)
Signed-off-by: Marc Jones <marc.jones@amd.com>
Acked-by: Marc Jones <marc.jones@amd.com>

git-svn-id: svn://coreboot.org/repository/coreboot-v3@955 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-10-27 23:16:17 +00:00
Ronald G. Minnich
cedf16ca69 Marc reviewed the v3 device tree code and we developed the set of
cleanups/fixes.

Fixup device tree code. Add/change methods as needed. 
This should help serengeti.
Signed-off-by: Ronald G. Minnich<rminnich@gmail.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Corey Osgood <corey.osgood@gmail.com>
Acked-by: Marc Jones <marc.jones@amd.com>


git-svn-id: svn://coreboot.org/repository/coreboot-v3@954 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-10-27 20:05:38 +00:00
Ronald G. Minnich
e3517187a0 Fix the sb600 and rs690 code in the same way we just fixed the amd8111.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>


git-svn-id: svn://coreboot.org/repository/coreboot-v3@911 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-10-09 15:11:52 +00:00
Ronald G. Minnich
b1dfc9858a This sb600 and rs690 support for a dbm690t that compiles. Stage0 is
23K, too large.    

dbe62 was tested and works i.e. this does no harm.

Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>



git-svn-id: svn://coreboot.org/repository/coreboot-v3@893 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-10-06 17:12:38 +00:00
Peter Stuge
e6a0cc07a7 Fix copypaste errors in the LPC PCI ID and the sata device_ops struct name.
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://coreboot.org/repository/coreboot-v3@884 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-10-03 04:20:04 +00:00
Ronald G. Minnich
d3ae8e7951 Let's add sb600 to the v3 repo this time.
My apologies. 

Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>



git-svn-id: svn://coreboot.org/repository/coreboot-v3@881 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-10-03 03:56:56 +00:00