Commit graph

10 commits

Author SHA1 Message Date
Ronald G. Minnich
a492ff7cc9 Kill off stage1_mtrr.c completely, and bring in mtrr.c for stage2 from v2.
Signed-off-by: Corey Osgood <corey.osgood@gmail.com>

It could use some cleanup, but looks good.

Acked-by: Peter Stuge <peter@stuge.se>

With some cleanup.

Acked-by: Ronald G. Minnich <rminnich@gmail.com>




git-svn-id: svn://coreboot.org/repository/coreboot-v3@1085 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-12-23 19:02:44 +00:00
Corey Osgood
758fecb860 Move OPTION_TABLE to a menu config option, and default it to enabled. This allows
a user/developer to disable the option table, so it doesn't overwrite whatever
the factory BIOS has written. Also fix building with OPTION_TABLE disabled.

Signed-off-by: Corey Osgood <corey.osgood@gmail.com>
Acked-by: Peter Stuge <peter@stuge.se>



git-svn-id: svn://coreboot.org/repository/coreboot-v3@1078 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-12-18 02:00:55 +00:00
Corey Osgood
4216c13386 Make C7/CN700 boot to memtest86, and pass that test. Booting is very slow, ~15min to get to a memtest
payload.

Signed-off-by: Corey Osgood <corey.osgood@gmail.com>
Acked-by: Corey Osgood <corey.osgood@gmail.com>



git-svn-id: svn://coreboot.org/repository/coreboot-v3@1077 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-12-17 21:17:01 +00:00
Corey Osgood
68529567e4 This patch:
* Moves non-DRAM early init code out of initram and into stage1, where 
it should have been in the first place
* Fixes an issue with GP3 timer causing system reboot (possibly not 
present in current svn, but was present in my local copy)
* Fixes serial garbage from stage1 on jetway j7f2
* Fixes ROM mapping for flash > 512k on vt8237
* Makes a couple minor whitespace changes
* Moves some function prototypes to the headers where they belong
* Nukes some phase2 hackery that belongs in phase4 (eventually)
* Comments out early_mtrr_init() for via/epia-cn, this breaks booting on 
jetway j7f2
* Moves troublesome SATA init code into stage1 - change of device class 
hangs coreboot
* Gets to vt8237 IDE phase6 init and dies on jetway/j7f2:
	Phase 6: Initializing devices...                                                
	Phase 6: Root Device init.                                                      
	Phase 6: PCI: 00:10.1 init.                                                     
	Primary IDE interface enabled                                                   
	Secondary IDE interface enabled 
	<hang>

Signed-off-by: Corey Osgood <corey.osgood@gmail.com>
Acked-by: Peter Stuge <peter@stuge.se>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>



git-svn-id: svn://coreboot.org/repository/coreboot-v3@1070 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-12-10 21:23:09 +00:00
Uwe Hermann
39d6231572 Fix EPIA-CN build in v3 by dropping duplicated stop_ap() definition (trivial).
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://coreboot.org/repository/coreboot-v3@1029 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-11-15 16:13:12 +00:00
Ronald G. Minnich
4964e25101 Get via to use standard mtrr init functions. Start to document them.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>




git-svn-id: svn://coreboot.org/repository/coreboot-v3@976 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-11-01 00:53:01 +00:00
Ronald G. Minnich
4f2df501f9 no PIRQ table
Make cmos.layout work with incomprehensible tool -- just turn off checksums.
Add static.c to list of files covered by kscope

Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>



git-svn-id: svn://coreboot.org/repository/coreboot-v3@975 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-10-31 22:43:02 +00:00
Peter Stuge
64fd88fced Add file that provides enable_smbus()
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>


git-svn-id: svn://coreboot.org/repository/coreboot-v3@974 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-10-31 22:04:29 +00:00
Ronald G. Minnich
cd5569e28e new files
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>



git-svn-id: svn://coreboot.org/repository/coreboot-v3@973 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-10-31 18:57:37 +00:00
Carl-Daniel Hailfinger
932667384b First parts of VIA EPIA-CN support.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>


git-svn-id: svn://coreboot.org/repository/coreboot-v3@946 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-10-23 01:18:30 +00:00