This is a potentially good pointer to where someone can take this.
While startup was working, BSP now explodes once the AP stops, while
BSP is doing startup IPI loop send #2. The code needs to be hardened; I
think use of the shared variables would really make it much more solid.
This would be a good undergrad student project if someone is looking for one.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@1145 f3766cd6-281f-0410-b1cd-43a5c92072e9
The reset value for NAND timings is the slowest possible for Flash interface.
Implement optionally setting it to a different value inside the NAND device.
Set it to appropriate values for Artec Group DBE61 and DBE62.
This results in a roughly two times quicker read time as measured by hdparm
for these boards.
Because we can not cast to southbridge_amd_cs5536_nand_config if the board dts
does not have an entry for the NAND device, this change proposes a method for
reasonably clean way to only optionally compile in support for certain devices:
If a board wants to support an optional device, its Kconfig entry can select
that configuration. If it's optional even across the same board, it can expose
a subconfig option of the board, that describes it and if chosen selects the
device config. The source code for that device is conditionally compiled only
if the Kconfig option gets enabled by the configuration for the board.
A requirement is that if the board configuration can enable a device, it is
contained in the boards dts file as well.
A perhaps better long-term alternative for this could be making dtc generate
preprocessor definitions for each device_configuration struct that it creates.
Then the source code file is always enabled, but that file can be wrapped
around a simple #ifdef check in its entirety.
Conversion to the alternative approach from the short-term Kconfig approach
proposed here should be relatively easy, as to not block inclusion of the
Kconfig approach in the short term.
Signed-off-by: Mart Raudsepp <mart.raudsepp@artecdesign.ee>
Acked-by: Marc Jones <marcj303@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@1138 f3766cd6-281f-0410-b1cd-43a5c92072e9
adaption of the v2 code, with significant cleanup and
simplification. It also works in CAR mode, and has no .bss or .data
usage. It provides for a way to provide AP POST codes to the BSP.
Since one common file with amd changed (lapic.h) I have build-tested this
against serengeti and it is fine.
It builds and I'll be testing it as soon as I can find the power supply for
the kontron (it got "borrowed").
Index: arch/x86/intel/core2/init_cpus.c
new file. Basically an adaptation of the v2 code to v3. All global variables
removed. One big change to note: there is a stack struct, and the
parameters to the secondary_start are struct members. Thus the BSP
can watch the AP, and, neater, the AP can POST to a shared variable
and the BSP can see how far it got.
Index: arch/x86/secondary.S
.S startup for AP.
Index: arch/x86/Kconfig
Delete a dependency.
Index: northbridge/intel/i945/reset_test.c
Add real cold boot detection.
Index: mainboard/kontron/986lcd-m/Makefile
Add some new build files.
Index: mainboard/kontron/986lcd-m/stage1.c
Get rid of ' in #warning that confused some tool.
Index: mainboard/kontron/986lcd-m/initram.c
Call init_cpus.
Index: mainboard/kontron/Kconfig
Turn off SMM for now.
Index: include/arch/x86/lapic.h
Correct a static inline declaration.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@1136 f3766cd6-281f-0410-b1cd-43a5c92072e9
that has already been done by the BSP. For single processor systems the CPU
flag is always 0, BSP. This code also moves the AP stop for K8 mainboards to
after memory setup so the AP's MTRRs can be setup to match system memory.
Signed-off-by: Marc Jones <marcj303@gmail.com>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@1129 f3766cd6-281f-0410-b1cd-43a5c92072e9
Signed-off-by: Mart Raudsepp <mart.raudsepp@artecdesign.ee>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@1122 f3766cd6-281f-0410-b1cd-43a5c92072e9
Signed-off-by: Mart Raudsepp <mart.raudsepp@artecdesign.ee>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@1121 f3766cd6-281f-0410-b1cd-43a5c92072e9
Signed-off-by: Mart Raudsepp <mart.raudsepp@artecdesign.ee>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@1120 f3766cd6-281f-0410-b1cd-43a5c92072e9
* Copying of files from other mainboards as a starting point:
amd/db800/Makefile
artecgroup/dbe62/cmos.layout
artecgroup/dbe62/dts
amd/db800/initram.c
artecgroup/dbe61/irq_tables.h
artecgroup/dbe62/stage1
* Kconfig integration. Behind CONFIG_EXPERIMENTAL for now, as the board is not in the market yet.
Signed-off-by: Mart Raudsepp <mart.raudsepp@artecdesign.ee>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@1119 f3766cd6-281f-0410-b1cd-43a5c92072e9
SPD_MIN_RAS_TO_CAS_DELAY is already set earlier in the list, so the alternative
constant tRCD in the end has no effect in the memory algorithm - remove them.
Signed-off-by: Mart Raudsepp <mart.raudsepp@artecdesign.ee>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@1115 f3766cd6-281f-0410-b1cd-43a5c92072e9
The device infrastructure already has an enabled bit, so we don't need to duplicate it in the current form.
cs5536.c:ide_init() is phase6_init, which is called only if the device is enabled, so if the device doesn't
exist, or the mainboard dts says "disabled;" for it, the init is not done and an extra conditional is not
necessary.
Adapt all cs5536 using mainboards to it (removing enable_ide variable) - artecgroup/dbe6[12] gets the whole
IDE device removed, which results in the ide_init() code not being ran as before (before it was called but
early return from enable_ide == 0, now it won't be called in the first place).
Signed-off-by: Mart Raudsepp <mart.raudsepp@artecdesign.ee>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@1114 f3766cd6-281f-0410-b1cd-43a5c92072e9
This implements a nand device, akin to the ide device to follow the coreboot-v3 device tree design better.
It allows us to do the IDE PCI header early enough in a clean way - the hide_vpci was called way too late
before - in phase6 of southbridge device, but we need the Flash header active instead of IDE in the VSA2
before bus scans happen, or the PCI device gets disabled in coreboot understanding by the time we get it
enabled in VSA2.
It makes NAND setup work better, but still not completely. There is a VSA2 bug for which I made a patch,
but waiting on a new binary to test if after that everything works or not. A quick hack to workaround the
VSA2 bug suggests something further will still need fixing. There are also more potential opportunities
to shuffle NAND code around to match v3 approach better, but that's a next step for me after NAND setup
actually works right in the current form.
Also corrected the documentation of ide_init() to match current reality.
Signed-off-by: Mart Raudsepp <mart.raudsepp@artecdesign.ee>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@1113 f3766cd6-281f-0410-b1cd-43a5c92072e9
It removes processors from the list of devices on the domain's bus so
that pci_scan_bus won't disable them, then scans for them, then puts
them back. There are lots of other ways to do this, but this one
seemed minimally invasive and ends up with a correct tree.
The dts fixups I should have put in with the other K8 patch for the
new resource allocator. I went to the v2 Config.lb files and tried to
get them as complete as possible.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@1109 f3766cd6-281f-0410-b1cd-43a5c92072e9
splits the domain and the memory controller functions into their respective
devices.
It also updates the dts for all the boards that use geodelx_video_mb.
Signed-off-by: Myles Watson <mylesgw@gmail.com>Acked-by: Marc Jones <marcj303@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@1103 f3766cd6-281f-0410-b1cd-43a5c92072e9
northbridge functions and makes devices children of the northbridge.
northbridge/amd/k8/domain.c:
Add the functions from k8/pci.c that belong to the domain. Add
support for physical link numbers in resource indices. Combine find_iopair
and find_mempair to find_regpair.
northbridge/amd/k8/pci.c:
Remove functions that went to the domain.
device/hypertransport.c:
Add support for HT connections from devices that aren't the bus
controller.
device/hypertransport.h:
Change the prototype of hypertransport_scan_chain.
northbridge/amd/k8/pci:
Take out bridge flag.
mainboard/amd/serengeti/stage1.c
Change first register usage.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@1094 f3766cd6-281f-0410-b1cd-43a5c92072e9
could be done.
northbridge/intel/i945/northbridge.dts
Remove bridge flag. Northbridges don't have children. The domains
they implement do.
northbridge/intel/i945/northbridge.c
Add IORESOURCE_BRIDGE flags and change the limit for MMIO to avoid ROM.
mainboard/kontron/986lcd-m/dts
Make PCI devices children of the domain and add a few devices.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@1093 f3766cd6-281f-0410-b1cd-43a5c92072e9
file-by-file changes:
dts:
There are no bus devices, remove it. Add the northbridge devices.
Fix susbsytem_vendor and subsystem_device.
southbridge/intel/i82371eb/ide:
Make the ide enabled by default.
northbridge/intel/i440bxemulation/i440bx.c:
1. Split ops into domain and northbridge
A. Domain should have bus ops, scan_bus, etc.
B. Northbridge should have ops for its own registers.
In this case it only needs read and set resources.
functions:
i440bx_read_resources - set up the IO and VGA resources. VGA is fixed.
i440bx_ram_resources - this should be called after resource assignment.
i440bx_set_resources - call pci_set_resources then i440bx_ram_resources.
i440bx_domain_read_resources - Set up system-wide resources, and
reserve space for the local APIC. I put the IOAPIC here too,
but it belongs somewhere in the southbridge.
i440bx_domain_set_resources - Mark the domain-specific resources as
stored (In a real device you'd probably need to set some
registers here.) Call phase4_set_resources for children.
southbridge/intel/i82371eb/i82371eb.c:
1. Add ISA read and set resources to reserve legacy IO space.
- Note that since it's subtractively decoded, it doesn't need
to be stored anywhere. It needs to be marked stored so
pci_set_resource doesn't try to store it.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@1092 f3766cd6-281f-0410-b1cd-43a5c92072e9
disk and attempt to boot a linux kernel.
Signed-off-by: Corey Osgood <corey.osgood@gmail.com>
Acked-by: Corey Osgood <corey.osgood@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@1087 f3766cd6-281f-0410-b1cd-43a5c92072e9
Signed-off-by: Corey Osgood <corey.osgood@gmail.com>
It could use some cleanup, but looks good.
Acked-by: Peter Stuge <peter@stuge.se>
With some cleanup.
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@1085 f3766cd6-281f-0410-b1cd-43a5c92072e9
have resulted in breaking the kontron port. I am trying to fix them.
In case there is any concern about the initialization:
this is a scalar auto being initialized.
The initialization is done in code. I have verified this both by checking
the object code and actually running it; this fix resolves a break introduced
at some point.
Other breakage remains: kontron now hangs here:
run_file returns with 0
Done RAM init code
Done printk() buffer move
disable_car entry
disable_car global_vars copy done
disable_car global_vars pointer adjusted
entering asm code now
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@1083 f3766cd6-281f-0410-b1cd-43a5c92072e9
a user/developer to disable the option table, so it doesn't overwrite whatever
the factory BIOS has written. Also fix building with OPTION_TABLE disabled.
Signed-off-by: Corey Osgood <corey.osgood@gmail.com>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@1078 f3766cd6-281f-0410-b1cd-43a5c92072e9
* Moves non-DRAM early init code out of initram and into stage1, where
it should have been in the first place
* Fixes an issue with GP3 timer causing system reboot (possibly not
present in current svn, but was present in my local copy)
* Fixes serial garbage from stage1 on jetway j7f2
* Fixes ROM mapping for flash > 512k on vt8237
* Makes a couple minor whitespace changes
* Moves some function prototypes to the headers where they belong
* Nukes some phase2 hackery that belongs in phase4 (eventually)
* Comments out early_mtrr_init() for via/epia-cn, this breaks booting on
jetway j7f2
* Moves troublesome SATA init code into stage1 - change of device class
hangs coreboot
* Gets to vt8237 IDE phase6 init and dies on jetway/j7f2:
Phase 6: Initializing devices...
Phase 6: Root Device init.
Phase 6: PCI: 00:10.1 init.
Primary IDE interface enabled
Secondary IDE interface enabled
<hang>
Signed-off-by: Corey Osgood <corey.osgood@gmail.com>
Acked-by: Peter Stuge <peter@stuge.se>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@1070 f3766cd6-281f-0410-b1cd-43a5c92072e9
Two unused variables, an incorrect pointer type, and two printf format
warnings.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@1068 f3766cd6-281f-0410-b1cd-43a5c92072e9
Whether SMM is added or not depends on the mainboard. To enable SMM,
the Kconfig variable SMM should be set, and the SMM variable should be
defined in the mainbard.
Also correct a type CONFIG_HPET should be HPET.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@1065 f3766cd6-281f-0410-b1cd-43a5c92072e9
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@1053 f3766cd6-281f-0410-b1cd-43a5c92072e9
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@1052 f3766cd6-281f-0410-b1cd-43a5c92072e9
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@1051 f3766cd6-281f-0410-b1cd-43a5c92072e9
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@1050 f3766cd6-281f-0410-b1cd-43a5c92072e9
Make statics non-static (we don't do buildrom any more)
Index: northbridge/intel/i945/raminit.c
remove snarf-o that left k8 in (I used wrong script I guess?)
Index: southbridge/intel/i82801gx/libsmbus.c
Corrections (minor)
Index: southbridge/intel/i82801gx/stage1_smbus.c
static to global
Index: mainboard/kontron/986lcd-m/stage1_debug.c
don't include statictree.c
Index: mainboard/kontron/986lcd-m/stage1.c
Remove functions that have to be in initram.
Index: mainboard/kontron/986lcd-m/initram.c
Add functions. This is all about splitting auto.c into stage1 and initram.
stage1 is very small and limited.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@1049 f3766cd6-281f-0410-b1cd-43a5c92072e9
pci_set_resources. There is no matching pci_bus_set_resources, so it's
confusing to see the dev function in the bus structures.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@1048 f3766cd6-281f-0410-b1cd-43a5c92072e9
device/pci_device.c:
Only update IDs if:
- The device is on the mainboard
- The device has a Vendor ID and Device ID
- The device has a set_subsystem function in ops_pci(dev)
util/dtc/flattree.c:
Make devices from the dts be on_mainboard.
If they're plugged in, they shouldn't be in the dts.
mainboard/amd/serengeti/dts:
Add subsystem_vendor and subsystem_device.
Build tested on Serengeti. Getting closer :)
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@1045 f3766cd6-281f-0410-b1cd-43a5c92072e9
I see no reason to have these memory work related debug calls commented out in the code, everyone should know what to locally temporarily add to debug this.
Signed-off-by: Mart Raudsepp <mart.raudsepp@artecdesign.ee>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@1037 f3766cd6-281f-0410-b1cd-43a5c92072e9
Parts of this patch (southbridge/intel/i82801gx/smi.c) were
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
The rest is
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@1031 f3766cd6-281f-0410-b1cd-43a5c92072e9
in.
include/device/pnp.h:
Add enable, val, and irq & drq structs.
superio/winbond/w83627hf/superio.c:
Change functions to operate on children.
Add device ID to ops.
Add enables to pnp_dev_info table.
Fill in dts values.
superio/winbond/w83627hf/dts:
Get rid of device number parameters.
Add config parameters so we know when they're set.
device/pnp_device.c:
Allocate devices as children to SuperIO.
mainboard/amd/serengeti/dts:
Move ioport so it's found. (Not its permanent resting place I hope.)
Add enables for KBC, SP1, and HWM to show it off.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@1027 f3766cd6-281f-0410-b1cd-43a5c92072e9
/home/rminnich/coreboot-v3/build/coreboot.initram_partiallylinked.o: section .data.rel.ro.local: dual_channel_slew_group_lookup.3242 single_channel_slew_group_lookup.3243
and
/home/rminnich/coreboot-v3/southbridge/intel/i82801gx/smbus.c:34: error: conflicting types for ‘smbus_read_byte’
include/device/smbus.h:56: error: previous declaration of ‘smbus_read_byte’ was here
we are working these. The second is much harder than it seems.
It concerns whether we put i2c devices (i.e. DRAM spd SEEPROMS) in the dts.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@1026 f3766cd6-281f-0410-b1cd-43a5c92072e9
Comment out not-yet-supplied initialize_cpus.
Fix missing ; in smbus.c
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@1025 f3766cd6-281f-0410-b1cd-43a5c92072e9
Lots more to do.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@1023 f3766cd6-281f-0410-b1cd-43a5c92072e9
It includes an ide option that has to be there, and fixes a CPU test in
Kconfig.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Myles Watson <mylesgw@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@1021 f3766cd6-281f-0410-b1cd-43a5c92072e9
Make statics non-static (we don't do buildrom any more)
Index: northbridge/intel/i945/raminit.c
remove snarf-o that left k8 in (I used wrong script I guess?)
Index: southbridge/intel/i82801gx/stage1_smbus.c
static to global
Index: mainboard/kontron/986lcd-m/stage1.c
Remove functions that have to be in initram.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@1020 f3766cd6-281f-0410-b1cd-43a5c92072e9
