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UPSTREAM: soc/intel/skylake/chip.h: Reorder declarations

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Place `tdp_pl2_override` above the FSP options as it's not an FSP option.

BUG=none
BRANCH=none
TEST=none

Change-Id: I01bda06d9ef57890891757ed94baf2e5bb4e2f8f
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 4a47e4b8ee
Original-Change-Id: Idff2b628d19ce1a80294b28c55c05ba4157d07e0
Original-Signed-off-by: Nico Huber <nico.huber@secunet.com>
Original-Reviewed-on: https://review.coreboot.org/19637
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Reviewed-by: Philippe Mathieu-Daud <philippe.mathieu.daude@gmail.com>
Original-Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://chromium-review.googlesource.com/528184
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
This commit is contained in:
Nico Huber 2017-05-09 16:14:36 +02:00 • committed by chrome-bot
parent b5d5a08fbd
commit ffecf56525
1 changed files with 3 additions and 2 deletions
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5
src/soc/intel/skylake/chip.h
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@ -94,6 +94,9 @@ struct soc_intel_skylake_config {
/* TCC activation offset */ /* TCC activation offset */
int tcc_offset; int tcc_offset;
/* PL2 Override value in Watts */
u32 tdp_pl2_override;
/* /*
* The following fields come from FspUpdVpd.h. * The following fields come from FspUpdVpd.h.
* These are configuration values that are passed to FSP during * These are configuration values that are passed to FSP during
@ -392,8 +395,6 @@ struct soc_intel_skylake_config {
* Setting to 0 (default) disables Heci1 and hides the device from OS * Setting to 0 (default) disables Heci1 and hides the device from OS
*/ */
u8 HeciEnabled; u8 HeciEnabled;
/* PL2 Override value in Watts */
u32 tdp_pl2_override;
u8 PmTimerDisabled; u8 PmTimerDisabled;
/* Intel Speed Shift Technology */ /* Intel Speed Shift Technology */
u8 speed_shift_enable; u8 speed_shift_enable;