mirror of
https://github.com/fail0verflow/switch-coreboot.git
synced 2025-05-04 01:39:18 -04:00
Closer to correct.
Detects SPD correctly, but the bank stuff really looks wrong.
This commit is contained in:
Ronald G. Minnich
parent
54e665686e
commit
ff291c1f67
1 changed files with 58 additions and 51 deletions
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@ -3,13 +3,16 @@
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***
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***/
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#define MAX_MEM_BANK $0x78
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#define LOAD_CURRENT_MCR mov (%esi),%al
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/*** sungeun jump to start ***/
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jmp raminit_start
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/***
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*** BEGIN TABLES
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***/
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dram_temp :
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mem_bank_reg_table :
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.byte 0x6c
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.byte 0x70
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.byte 0x74
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@ -97,7 +100,7 @@ internal_bank_tbl:
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mov %dl,%al ; \
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and $3,%al ; \
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mov $0x0cfc,%dx ; \
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add %dl,%al ; \
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add %al,%dl ; \
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mov %cl,%al ; \
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outb %al,%dx
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@ -144,7 +147,7 @@ internal_bank_tbl:
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#define save_dram_type \
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mov %sp,%di ; \
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mov %esi,%eax ; \
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subl $dram_temp, %eax ; \
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subl $mem_bank_reg_table, %eax ; \
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mov $2,%dl ; \
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mul %dl ; \
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addl $0x94,%eax ; \
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@ -169,12 +172,12 @@ internal_bank_tbl:
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mov $0x0100,%cx ; \
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save_dram_type ; \
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ror $16,%edi ; \
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mov (%esi),%al ; \
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LOAD_CURRENT_MCR ; \
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add $3,%al ; \
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pci_read_byte ; \
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and $0b11100111,%al ; \
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mov %al,%cl ; \
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mov (%esi),%al ; \
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LOAD_CURRENT_MCR ; \
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add $3,%al ; \
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pci_write_byte ; \
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mov %di,%sp
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@ -207,12 +210,12 @@ internal_bank_tbl:
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#define DISABLE_BLOCK \
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mov (%esi),%al ; \
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LOAD_CURRENT_MCR ; \
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pci_write_dword ; \
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and $0x0f87fffff,%eax ; \
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xor %di,%di ; \
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mov %eax,%edi ; \
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mov (%esi),%al ; \
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LOAD_CURRENT_MCR ; \
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pci_read_dword
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@ -226,41 +229,44 @@ internal_bank_tbl:
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***/
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raminit_start:
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mov $0x81,%ax
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mov $0x7f00,%cx
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mov $0x7f00,%cx /*** disable SMA mode ***/
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pci_read_write_byte
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mov $0x82,%ax
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mov $0xff10,%cx
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mov $0xff10,%cx /*** set 3 DIMMs, no ECC ***/
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pci_read_write_byte
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mov $0x84,%ax
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mov $0xfe00,%cx
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mov $0xfe00,%cx /*** set 3 DIMMs, no ECC ***/
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pci_read_write_byte
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movl $dram_temp,%esi
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/*** initialize, load table, zero %ecx, %ebx ***/
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movl $mem_bank_reg_table,%esi
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xor %ecx,%ecx
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xor %ebx,%ebx
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/*** main loop ***/
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detect_block_again:
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or $0x10000,%ebx
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or $0x10000,%ebx /*** for even bank ***/
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xor %bx,%bx
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mov (%esi),%al
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add $3,%al
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LOAD_CURRENT_MCR /*** current memory control register ***/
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add $3,%al /*** point to upper byte of MCR ***/
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mov %cx,%di
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mov $0x0ee,%cl
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mov $0x0ee,%cl /*** EDO DRAM ***/
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pci_write_byte
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mov (%esi),%al
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LOAD_CURRENT_MCR
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add $2,%al
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mov $0x064,%cl
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mov $0x064,%cl /*** 256M col=12 bits ***/
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pci_write_byte
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mov %di,%cx
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jmp detect_ma_size
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odd_bank_detect:
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shl $3,%bx
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and $(~0x10000),%ebx
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mov (%esi),%al
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LOAD_CURRENT_MCR
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add $3,%al
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mov $0x0e9,%cl
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pci_write_byte
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mov (%esi),%al
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LOAD_CURRENT_MCR
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add $2,%al
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mov $0x0e4,%cl
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pci_write_byte
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@ -268,6 +274,7 @@ detect_ma_size:
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/***
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*** sungeun *** BEGIN "inlined" macro DETECT_DRAM_TYPE
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***/
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/*** standard EDO dram test ***/
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movl $0x055555555,%es:(0x0)
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movl $0x0aaaaaaaa,%es:(0x8)
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cmpl $0x55555555,%es:(0)
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@ -283,17 +290,17 @@ detect_ma_size:
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jmp dram_type_detect_end
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detect_sdram:
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mov $0x7e,%ax
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mov $0xf700, %cx
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mov $0xf700, %cx /*** turn off EDO detect ***/
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pci_read_write_byte
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mov (%esi),%al
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LOAD_CURRENT_MCR
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mov %al,%ah
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mov $0x42,%al
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cmos_data_in
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test $0b00010000,%al
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mov %ah,%al
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jz cas_2
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mov (%esi),%al
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pci_write_dword
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/*** jz cas_2 *** always slow ***/
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LOAD_CURRENT_MCR
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pci_read_dword /*** changed from pci_write_dword ***/
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mov %eax,%edi
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and $0x00000fffc,%edi
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test $0x010000,%ebx
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@ -304,8 +311,8 @@ detect_sdram:
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or $0x0f1e40000,%edi
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jmp configure_sdram_type
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cas_2:
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mov (%esi),%al
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pci_write_dword
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LOAD_CURRENT_MCR
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pci_read_dword /*** changed from pci_write_dword ***/
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mov %eax,%edi
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and $0x00000fffc,%edi
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test $0x010000,%ebx
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@ -315,10 +322,10 @@ cas_2:
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1:
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or $0x0d1e40000,%edi
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configure_sdram_type:
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mov (%esi),%al
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pci_read_dword
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mov $1000,%ax
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1:
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LOAD_CURRENT_MCR
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pci_write_dword /*** changed from pci_read_dword ***/
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mov $0xFFFF,%ax /*** mov $1000,%ax ***/
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1: /*** timing loop *** wait for dram to finish configuration ***/
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dec %ax
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jnz 1b
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movl $0x055555555,%es:(0x0)
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@ -335,19 +342,19 @@ configure_sdram_type:
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save_dram_type
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jmp dram_type_detect_end
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chk_vc_sdram_type:
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mov (%esi),%al
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LOAD_CURRENT_MCR
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pci_write_dword
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mov %eax,%edi
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and $0x0e7ffffff,%edi
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mov (%esi),%al
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LOAD_CURRENT_MCR
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pci_read_dword
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mov $0x7e,%ax
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mov $0xf700,%cx
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pci_read_write_byte
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mov (%esi),%al
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LOAD_CURRENT_MCR
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pci_write_dword
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mov %eax,%edi
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mov (%esi),%al
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LOAD_CURRENT_MCR
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test $0x010000,%ebx
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jz 1f
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and $0x00000d7f0,%edi
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@ -357,7 +364,7 @@ chk_vc_sdram_type:
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and $0x00000d7f0,%edi
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or $0x0f9e20000,%edi
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configure_vc_sdram_type:
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mov (%esi),%al
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LOAD_CURRENT_MCR
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pci_read_dword
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mov $1000,%ax
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1:
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@ -402,7 +409,7 @@ dram_type_detect_end:
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jz a_sub_end
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cmp $0x00,%ah
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jnz no_sdram
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mov (%esi),%al
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LOAD_CURRENT_MCR
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pci_write_dword
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mov %eax,%edi
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and $0x00000ffff,%edi
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@ -429,7 +436,7 @@ set_cas_end:
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jz set_single
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or $1,%edi
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set_single:
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mov (%esi),%al
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LOAD_CURRENT_MCR
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pci_read_dword
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jmp detect_block_again_end
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no_sdram:
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@ -520,14 +527,14 @@ memory_sizing_sub:
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shr $20,%eax
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mov %al,%cl
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configure_ma:
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mov (%esi),%al
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LOAD_CURRENT_MCR
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add $2,%al
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pci_read_byte
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and $0x0f0,%al
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and $0x0f,%cl
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or %cl,%al
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mov %al,%cl
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mov (%esi),%al
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LOAD_CURRENT_MCR
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add $2,%al
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pci_write_byte
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@ -620,20 +627,20 @@ determine_bank_number:
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test $0x40000,%ebx
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jnz configure_internal_bank_end
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mov %cx,%di
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mov (%esi),%al
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LOAD_CURRENT_MCR
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add $1,%al
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pci_read_byte
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and $0x0ef,%al
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mov %al,%cl
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mov (%esi),%al
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LOAD_CURRENT_MCR
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add $1,%al
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pci_write_byte
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mov (%esi),%al
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LOAD_CURRENT_MCR
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pci_read_byte
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and $0x0fc,%al
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or $1,%al
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mov %al,%cl
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mov (%esi),%al
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LOAD_CURRENT_MCR
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pci_write_byte
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mov %di,%cx
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test $0x10000,%ebx
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@ -663,11 +670,11 @@ what_memory_ma:
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mov %di,%si
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jz i_4_bank
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mov %cx,%di
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mov (%esi),%al
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LOAD_CURRENT_MCR
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pci_read_byte
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and $0x0fc,%al
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mov %al,%cl
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mov (%esi),%al
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LOAD_CURRENT_MCR
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pci_write_byte
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mov %di,%cx
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i_4_bank:
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@ -683,7 +690,7 @@ EDO_T:
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*** sungeun *** END "inlined" macro MEMORY_SIZING
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***/
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mov (%esi),%al
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LOAD_CURRENT_MCR
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add $2,%al
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mov %bx,%di
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pci_read_byte
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@ -692,7 +699,7 @@ EDO_T:
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and $0x8f,%al
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or %di,%ax
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mov %al,%cl
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mov (%esi),%al
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LOAD_CURRENT_MCR
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add $2,%al
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pci_write_byte
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/***
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@ -736,7 +743,7 @@ configure_memory_block:
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/***
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*** sungeun *** BEGIN "inlined" macro CONFIGURE_MEMORY
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***/
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movl $dram_temp,%esi
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movl $mem_bank_reg_table,%esi
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mov (%esi),%dl
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mov $0x094,%bl
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configure_next:
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@ -756,16 +763,16 @@ configure_next:
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jz 1f
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or $0x03,%di
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1:
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mov (%esi),%al
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LOAD_CURRENT_MCR
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pci_write_dword
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and $0x0f87fffff,%eax
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shl $23,%edi
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or %edi,%eax
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mov %eax,%edi
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mov (%esi),%al
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LOAD_CURRENT_MCR
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pci_read_dword
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inc %si
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cmpb $0x78,(%esi)
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cmpb MAX_MEM_BANK,(%esi)
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jnz configure_next
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/***
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*** sungeun *** END "inlined" macro CONFIGURE_MEMORY
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