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UPSTREAM: src/include: Add required space before opening parenthesis '('

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BUG=None
BRANCH=None
TEST=None

Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/16285
Tested-by: build bot (Jenkins)
Reviewed-by: Omar Pakker

Change-Id: I307d37cdf2647467d4c88dfa4be5c66c8587202e
Reviewed-on: https://chromium-review.googlesource.com/377613
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Elyes HAOUAS 2016-08-21 17:28:20 +02:00 • committed by chrome-bot
parent d589ff9726
commit fd89b1821b
1 changed files with 2 additions and 2 deletions
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4
src/include/cpu/amd/model_fxx_rev.h
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@ -73,7 +73,7 @@ static inline int is_e0_later_in_bsp(int nodeid)
if (IS_ENABLED(CONFIG_K8_REV_F_SUPPORT))
return 1;
if(nodeid==0) { // we don't need to do that for node 0 in core0/node0
if (nodeid==0) { // we don't need to do that for node 0 in core0/node0
return !is_cpu_pre_e0();
}
// d0 will be treated as e0 with this methods, but the d0 nb_cfg_54 always 0
@ -85,7 +85,7 @@ static inline int is_e0_later_in_bsp(int nodeid)
pci_write_config32(dev, 0x80, val);
val = pci_read_config32(dev, 0x80);
e0_later = !!(val & (1<<3));
if(e0_later) { // pre_e0 bit 3 always be 0 and can not be changed
if (e0_later) { // pre_e0 bit 3 always be 0 and can not be changed
pci_write_config32(dev, 0x80, val_old); // restore it
}