mirror of
https://github.com/fail0verflow/switch-coreboot.git
synced 2025-05-04 01:39:18 -04:00
irq tables for the smartcore-p5
This commit is contained in:
Ronald G. Minnich
parent
595220a3ab
commit
fd1115297e
1 changed files with 36 additions and 157 deletions
|
|
@ -1,163 +1,42 @@
|
|||
#include <subr.h>
|
||||
/* This file was generated by getpir.c, do not modify!
|
||||
(but if you do, please run checkpir on it to verify)
|
||||
Contains the IRQ Routing Table dumped directly from your memory , wich BIOS sets up
|
||||
|
||||
Documentation at : http://www.microsoft.com/hwdev/busbios/PCIIRQ.HTM
|
||||
*/
|
||||
|
||||
#include <arch/pirq_routing.h>
|
||||
|
||||
/*
|
||||
* This table must be located between 0x000f0000 and 0x000fffff.
|
||||
* By defining it as a const it gets located in the code segment
|
||||
* and therefore inside the necessary 64K block. -tds
|
||||
*/
|
||||
|
||||
#define USB_DEVFN (PIIX4_DEVFN+2)
|
||||
#define SUM_REST 0x00 /* ...just happens to be 0 */
|
||||
#define CHECKSUM (0x00-(SUM_REST+PIIX4_DEVFN+USB_DEVFN))
|
||||
|
||||
// In spite of the comment below I have located this in the
|
||||
// gigabit tree until we work this all out -- RGM
|
||||
/*
|
||||
* This table should work for most systems using the PIIX4
|
||||
* southbridge that have 4 PCI slots.
|
||||
*
|
||||
* I recall that the 440GX board that Ron was using had
|
||||
* the PIIX4 at a different location. This will effect the
|
||||
* devfn of the router and USB controller as well as the
|
||||
* checksum. Hopefully the defines will allow this to
|
||||
* be a bit more portable.
|
||||
* -tds
|
||||
*/
|
||||
|
||||
const struct irq_routing_table intel_irq_routing_table = {
|
||||
PIRQ_SIGNATURE, /* u32 signature */
|
||||
PIRQ_VERSION, /* u16 version */
|
||||
32+16*5, /* u16 size - size of entire table struct */
|
||||
0, /* u8 rtr_bus - router bus */
|
||||
PIIX4_DEVFN, /* u8 rtr_devfn - router devfn */
|
||||
0x0e00, /* u16 exclusive_irqs - mask of IRQs for PCI use */
|
||||
0x8086, /* u16 rtr_vendor - router vendor id */
|
||||
0x7110, /* u16 rtr_devfn - router device id */
|
||||
0, /* u8 miniport_data - "crap" */
|
||||
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */
|
||||
CHECKSUM, /* u8 checksum - mod 256 checksum must give zero */
|
||||
/* struct irq_info slots[0] */
|
||||
{
|
||||
{
|
||||
0, /* u8 bus */
|
||||
USB_DEVFN, /* u8 devfn for USB controller */
|
||||
{
|
||||
PIRQ_SIGNATURE, /* u32 signature */
|
||||
PIRQ_VERSION, /* u16 version */
|
||||
32+16*18, /* there can be total 18 devices on the bus */
|
||||
0, /* Where the interrupt router lies (bus) */
|
||||
0x38, /* Where the interrupt router lies (dev) */
|
||||
0, /* IRQs devoted exclusively to PCI usage */
|
||||
0x8086, /* Vendor */
|
||||
0x122e, /* Device */
|
||||
0, /* Crap (miniport) */
|
||||
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */
|
||||
0x8a, /* u8 checksum , this hase to set to some value that would give 0 after the sum of all bytes for this structure (including checksum) */
|
||||
{
|
||||
0x00, /* u8 link - IRQ line ID */
|
||||
0x0000, /* u16 bitmap - Available IRQs */
|
||||
},
|
||||
{
|
||||
0x00, /* u8 link - IRQ line ID */
|
||||
0x0000, /* u16 bitmap - Available IRQs */
|
||||
},
|
||||
{
|
||||
0x00, /* u8 link - IRQ line ID */
|
||||
0x0000, /* u16 bitmap - Available IRQs */
|
||||
},
|
||||
{
|
||||
0x63, /* u8 link - IRQ line ID */
|
||||
0xdef8, /* u16 bitmap - Available IRQs */
|
||||
{0,0x80, {{0x60, 0xdef8}, {0x61, 0xdef8}, {0x62, 0xdef8}, {0x63, 0xdef8}}, 0, 0},
|
||||
{0,0x48, {{0x60, 0xdef8}, {0x61, 0xdef8}, {0x62, 0xdef8}, {0x63, 0xdef8}}, 0x1, 0},
|
||||
{0,0x50, {{0x61, 0xdef8}, {0x62, 0xdef8}, {0x63, 0xdef8}, {0x60, 0xdef8}}, 0x2, 0},
|
||||
{0,0x58, {{0x62, 0xdef8}, {0x63, 0xdef8}, {0x60, 0xdef8}, {0x61, 0xdef8}}, 0x3, 0},
|
||||
{0,0x60, {{0x63, 0xdef8}, {0x60, 0xdef8}, {0x61, 0xdef8}, {0x62, 0xdef8}}, 0x4, 0},
|
||||
{0,0x38, {{0x60, 0xdef8}, {0x61, 0xdef8}, {0x62, 0xdef8}, {0x63, 0xdef8}}, 0, 0},
|
||||
{0,0xa0, {{0, 0xdef8}, {0, 0xdef8}, {0, 0xdef8}, {0, 0xdef8}}, 0, 0},
|
||||
{0,0x88, {{0x62, 0xdef8}, {0x63, 0xdef8}, {0, 0xdef8}, {0, 0xdef8}}, 0, 0},
|
||||
{0,0x98, {{0x61, 0xdef8}, {0, 0xdef8}, {0, 0xdef8}, {0, 0xdef8}}, 0, 0},
|
||||
{0,0x90, {{0x60, 0xdef8}, {0, 0xdef8}, {0, 0xdef8}, {0, 0xdef8}}, 0, 0},
|
||||
{0,0x78, {{0x61, 0xdef8}, {0x62, 0xdef8}, {0x63, 0xdef8}, {0x60, 0xdef8}}, 0, 0},
|
||||
{0x1,0x48, {{0x60, 0xdef8}, {0x61, 0xdef8}, {0x62, 0xdef8}, {0x63, 0xdef8}}, 0x1, 0},
|
||||
{0x1,0x50, {{0x61, 0xdef8}, {0x62, 0xdef8}, {0x63, 0xdef8}, {0x60, 0xdef8}}, 0x2, 0},
|
||||
{0x1,0x58, {{0x62, 0xdef8}, {0x63, 0xdef8}, {0x60, 0xdef8}, {0x61, 0xdef8}}, 0x3, 0},
|
||||
{0x1,0x60, {{0x63, 0xdef8}, {0x60, 0xdef8}, {0x61, 0xdef8}, {0x62, 0xdef8}}, 0x4, 0},
|
||||
{0x1,0x68, {{0x60, 0xdef8}, {0x61, 0xdef8}, {0x62, 0xdef8}, {0x63, 0xdef8}}, 0x5, 0},
|
||||
{0x1,0x70, {{0x61, 0xdef8}, {0x62, 0xdef8}, {0x63, 0xdef8}, {0x60, 0xdef8}}, 0x6, 0},
|
||||
{0x1,0x78, {{0x62, 0xdef8}, {0x63, 0xdef8}, {0x60, 0xdef8}, {0x61, 0xdef8}}, 0x7, 0},
|
||||
}
|
||||
},
|
||||
0, /* u8 slot */
|
||||
0, /* u8 rfu */
|
||||
},
|
||||
{
|
||||
0, /* u8 bus */
|
||||
0x40, /* u8 devfn for PCI slot 1 */
|
||||
{
|
||||
{
|
||||
0x60, /* u8 link - IRQ line ID */
|
||||
0xdef8, /* u16 bitmap - Available IRQs */
|
||||
},
|
||||
{
|
||||
0x61, /* u8 link - IRQ line ID */
|
||||
0xdef8, /* u16 bitmap - Available IRQs */
|
||||
},
|
||||
{
|
||||
0x62, /* u8 link - IRQ line ID */
|
||||
0xdef8, /* u16 bitmap - Available IRQs */
|
||||
},
|
||||
{
|
||||
0x63, /* u8 link - IRQ line ID */
|
||||
0xdef8, /* u16 bitmap - Available IRQs */
|
||||
}
|
||||
},
|
||||
1, /* u8 slot */
|
||||
0, /* u8 rfu */
|
||||
},
|
||||
{
|
||||
0, /* u8 bus */
|
||||
0x48, /* u8 devfn for PCI slot 2 */
|
||||
{
|
||||
{
|
||||
0x61, /* u8 link - IRQ line ID */
|
||||
0xdef8, /* u16 bitmap - Available IRQs */
|
||||
},
|
||||
{
|
||||
0x62, /* u8 link - IRQ line ID */
|
||||
0xdef8, /* u16 bitmap - Available IRQs */
|
||||
},
|
||||
{
|
||||
0x63, /* u8 link - IRQ line ID */
|
||||
0xdef8, /* u16 bitmap - Available IRQs */
|
||||
},
|
||||
{
|
||||
0x60, /* u8 link - IRQ line ID */
|
||||
0xdef8, /* u16 bitmap - Available IRQs */
|
||||
}
|
||||
},
|
||||
2, /* u8 slot */
|
||||
0, /* u8 rfu */
|
||||
},
|
||||
{
|
||||
0, /* u8 bus */
|
||||
0x50, /* u8 devfn for PCI slot 3 */
|
||||
{
|
||||
{
|
||||
0x62, /* u8 link - IRQ line ID */
|
||||
0xdef8, /* u16 bitmap - Available IRQs */
|
||||
},
|
||||
{
|
||||
0x63, /* u8 link - IRQ line ID */
|
||||
0xdef8, /* u16 bitmap - Available IRQs */
|
||||
},
|
||||
{
|
||||
0x60, /* u8 link - IRQ line ID */
|
||||
0xdef8, /* u16 bitmap - Available IRQs */
|
||||
},
|
||||
{
|
||||
0x61, /* u8 link - IRQ line ID */
|
||||
0xdef8, /* u16 bitmap - Available IRQs */
|
||||
}
|
||||
},
|
||||
3, /* u8 slot */
|
||||
0, /* u8 rfu */
|
||||
},
|
||||
{
|
||||
0, /* u8 bus */
|
||||
0x58, /* u8 devfn for PCI slot 4 */
|
||||
{
|
||||
{
|
||||
0x63, /* u8 link - IRQ line ID */
|
||||
0xdef8, /* u16 bitmap - Available IRQs */
|
||||
},
|
||||
{
|
||||
0x60, /* u8 link - IRQ line ID */
|
||||
0xdef8, /* u16 bitmap - Available IRQs */
|
||||
},
|
||||
{
|
||||
0x61, /* u8 link - IRQ line ID */
|
||||
0xdef8, /* u16 bitmap - Available IRQs */
|
||||
},
|
||||
{
|
||||
0x62, /* u8 link - IRQ line ID */
|
||||
0xdef8, /* u16 bitmap - Available IRQs */
|
||||
}
|
||||
},
|
||||
4, /* u8 slot */
|
||||
0, /* u8 rfu */
|
||||
}
|
||||
}
|
||||
};
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue