From fbc1c13f9ab808fc907b2e3f9bde1d09f92980f1 Mon Sep 17 00:00:00 2001 From: Lin Huang Date: Thu, 7 Jul 2016 19:19:48 +0800 Subject: [PATCH] rockchip/rk3399: set CA drive strength to 48ohms As shown in testing, if CA use 34.3ohms drive strength, it leads to an overshoot. To fix this, change the drive strength to 48 ohms. BRANCH=none BUG=chrome-os-partner:54871 TEST=run "stressapptest -M 1024 -s 1000" on kevin board and pass Change-Id: I231f5b1bd45ff262686fbacbaf119a8a57fad27b Signed-off-by: Lin Huang Reviewed-on: https://chromium-review.googlesource.com/358761 Commit-Ready: Dan Shi Tested-by: Caesar Wang Reviewed-by: Julius Werner --- src/soc/rockchip/rk3399/sdram.c | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/src/soc/rockchip/rk3399/sdram.c b/src/soc/rockchip/rk3399/sdram.c index 293a0f2108..c3db47bcf6 100644 --- a/src/soc/rockchip/rk3399/sdram.c +++ b/src/soc/rockchip/rk3399/sdram.c @@ -182,32 +182,39 @@ static void set_ds_odt(u32 channel, u32 tsel_idle_en, tsel_wr_en, tsel_rd_en; u32 tsel_idle_select_p, tsel_wr_select_p, tsel_rd_select_p; + u32 ca_tsel_wr_select_p, ca_tsel_wr_select_n; u32 tsel_idle_select_n, tsel_wr_select_n, tsel_rd_select_n; u32 reg_value; if (sdram_params->dramtype == LPDDR4) { tsel_rd_select_p = PHY_DRV_ODT_Hi_Z; tsel_wr_select_p = PHY_DRV_ODT_40; + ca_tsel_wr_select_p = PHY_DRV_ODT_40; tsel_idle_select_p = PHY_DRV_ODT_Hi_Z; tsel_rd_select_n = PHY_DRV_ODT_240; tsel_wr_select_n = PHY_DRV_ODT_40; + ca_tsel_wr_select_n = PHY_DRV_ODT_40; tsel_idle_select_n = PHY_DRV_ODT_240; } else if (sdram_params->dramtype == LPDDR3) { tsel_rd_select_p = PHY_DRV_ODT_240; tsel_wr_select_p = PHY_DRV_ODT_34_3; + ca_tsel_wr_select_p = PHY_DRV_ODT_48; tsel_idle_select_p = PHY_DRV_ODT_240; tsel_rd_select_n = PHY_DRV_ODT_Hi_Z; tsel_wr_select_n = PHY_DRV_ODT_34_3; + ca_tsel_wr_select_n = PHY_DRV_ODT_48; tsel_idle_select_n = PHY_DRV_ODT_Hi_Z; } else { tsel_rd_select_p = PHY_DRV_ODT_240; tsel_wr_select_p = PHY_DRV_ODT_34_3; + ca_tsel_wr_select_p = PHY_DRV_ODT_34_3; tsel_idle_select_p = PHY_DRV_ODT_240; tsel_rd_select_n = PHY_DRV_ODT_240; tsel_wr_select_n = PHY_DRV_ODT_34_3; + ca_tsel_wr_select_n = PHY_DRV_ODT_34_3; tsel_idle_select_n = PHY_DRV_ODT_240; } @@ -243,7 +250,7 @@ static void set_ds_odt(u32 channel, clrsetbits_le32(&denali_phy[391], 0xffffff, reg_value); /* phy_adr_tsel_select_ 8bits DENALI_PHY_544/672/800 offset_0 */ - reg_value = tsel_wr_select_n | (tsel_wr_select_p << 0x4); + reg_value = ca_tsel_wr_select_n | (ca_tsel_wr_select_p << 0x4); clrsetbits_le32(&denali_phy[544], 0xff, reg_value); clrsetbits_le32(&denali_phy[672], 0xff, reg_value); clrsetbits_le32(&denali_phy[800], 0xff, reg_value);