From fb0699a9ec34944293984239236d987723b499fb Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jonathan=20Neusch=C3=A4fer?= Date: Tue, 9 Aug 2016 02:07:12 +0200 Subject: [PATCH] UPSTREAM: arch/riscv: Fix the page table setup code In particular: - Fix the condition of the loop that fills the mid-level page table - Adhere to the format of sptbr BUG=None BRANCH=None TEST=None Signed-off-by: Jonathan Neuschfer Reviewed-on: https://review.coreboot.org/16120 Reviewed-by: Ronald G. Minnich Change-Id: I575093445edfdf5a8f54b0f8622ff0e89f77ccec Reviewed-on: https://chromium-review.googlesource.com/369148 Commit-Ready: Furquan Shaikh Tested-by: Furquan Shaikh Reviewed-by: Aaron Durbin --- src/arch/riscv/virtual_memory.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/src/arch/riscv/virtual_memory.c b/src/arch/riscv/virtual_memory.c index 385a5fd319..bbbba7a690 100644 --- a/src/arch/riscv/virtual_memory.c +++ b/src/arch/riscv/virtual_memory.c @@ -74,7 +74,9 @@ void init_vm(uintptr_t virtMemStart, uintptr_t physMemStart, uintptr_t pageTable root_pt[(1<> RISCV_PGSHIFT) + i); // fill the middle page table - for (uintptr_t vaddr = virtMemStart, paddr = physMemStart; paddr < memorySize; vaddr += SUPERPAGE_SIZE, paddr += SUPERPAGE_SIZE) { + for (uintptr_t vaddr = virtMemStart, paddr = physMemStart; + paddr < physMemStart + memorySize; + vaddr += SUPERPAGE_SIZE, paddr += SUPERPAGE_SIZE) { int l2_shift = RISCV_PGLEVEL_BITS + RISCV_PGSHIFT; size_t l2_idx = (virtMemStart >> l2_shift) & ((1 << RISCV_PGLEVEL_BITS)-1); l2_idx += ((vaddr - virtMemStart) >> l2_shift); @@ -95,7 +97,8 @@ void init_vm(uintptr_t virtMemStart, uintptr_t physMemStart, uintptr_t pageTable mb(); root_page_table = root_pt; - write_csr(sptbr, root_pt); + uintptr_t ptbr = ((uintptr_t) root_pt) >> RISCV_PGSHIFT; + write_csr(sptbr, ptbr); } void initVirtualMemory(void) {