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UPSTREAM: intel/apollolake: Disable setting of EISS bit in FSP

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chrome-os-partner:54589

Change-Id: I5bdd417ed2f7ec013aeb8a0d4a9de57b1ad564a1
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/15276
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/354993
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
This commit is contained in:
Furquan Shaikh 2016-06-20 16:08:42 -07:00 • committed by chrome-bot
parent 52db525881
commit f7f03b0e28
1 changed files with 3 additions and 0 deletions
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3
src/soc/intel/apollolake/chip.c
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@ -138,6 +138,9 @@ void platform_fsp_silicon_init_params_cb(struct FSPS_UPD *silupd)
silconfig->P2sbBase = P2SB_BAR;
silconfig->IshEnable = cfg->integrated_sensor_hub_enable;
/* Disable setting of EISS bit in FSP. */
silconfig->SpiEiss = 0;
}
struct chip_operations soc_intel_apollolake_ops = {