mirror of
https://github.com/fail0verflow/switch-coreboot.git
synced 2025-05-04 01:39:18 -04:00
This patch fixes white space in northbridge/amd/pci with the help of indent.
Signed-off-by: Myles Watson <mylesgw@gmail.com> Acked-by: Myles Watson <mylesgw@gmail.com> git-svn-id: svn://coreboot.org/repository/coreboot-v3@1042 f3766cd6-281f-0410-b1cd-43a5c92072e9
This commit is contained in:
Myles Watson
parent
4e9c6f3669
commit
f75b0fe103
1 changed files with 242 additions and 224 deletions
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@ -47,163 +47,166 @@
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#include <lapic.h>
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#define FX_DEVS 8
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extern struct device * __f0_dev[FX_DEVS];
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extern struct device *__f0_dev[FX_DEVS];
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extern void get_fx_devs(void);
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u32 f1_read_config32(unsigned int reg);
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void f1_write_config32(unsigned int reg, u32 value);
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unsigned int amdk8_nodeid(struct device * dev);
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unsigned int amdk8_nodeid(struct device *dev);
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static unsigned int amdk8_scan_chain(struct device * dev, unsigned nodeid, unsigned link, unsigned sblink, unsigned int max, unsigned offset_unitid)
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static unsigned int amdk8_scan_chain(struct device *dev, unsigned nodeid,
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unsigned link, unsigned sblink,
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unsigned int max, unsigned offset_unitid)
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{
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u32 link_type;
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int i;
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u32 busses, config_busses;
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unsigned free_reg, config_reg;
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unsigned ht_unitid_base[4]; // here assume only 4 HT device on chain
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unsigned max_bus;
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unsigned min_bus;
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unsigned max_devfn;
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printk(BIOS_SPEW, "amdk8_scan_chain link %x\n",link);
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dev->link[link].cap = 0x80 + (link *0x20);
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do {
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link_type = pci_read_config32(dev, dev->link[link].cap + 0x18);
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} while(link_type & ConnectionPending);
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if (!(link_type & LinkConnected)) {
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return max;
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u32 link_type;
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int i;
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u32 busses, config_busses;
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unsigned free_reg, config_reg;
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unsigned ht_unitid_base[4]; // here assume only 4 HT device on chain
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unsigned max_bus;
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unsigned min_bus;
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unsigned max_devfn;
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printk(BIOS_SPEW, "amdk8_scan_chain link %x\n", link);
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dev->link[link].cap = 0x80 + (link * 0x20);
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do {
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link_type = pci_read_config32(dev, dev->link[link].cap + 0x18);
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} while (link_type & ConnectionPending);
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if (!(link_type & LinkConnected)) {
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return max;
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}
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printk(BIOS_DEBUG, "amdk8_scan_chain: link %d is connected\n", link);
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do {
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link_type = pci_read_config32(dev, dev->link[link].cap + 0x18);
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} while (!(link_type & InitComplete));
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if (!(link_type & NonCoherent)) {
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return max;
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}
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/* See if there is an available configuration space mapping
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* register in function 1.
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*/
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free_reg = 0;
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for (config_reg = 0xe0; config_reg <= 0xec; config_reg += 4) {
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u32 config;
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config = f1_read_config32(config_reg);
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if (!free_reg && ((config & 3) == 0)) {
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free_reg = config_reg;
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continue;
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}
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printk(BIOS_DEBUG, "amdk8_scan_chain: link %d is connected\n", link);
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do {
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link_type = pci_read_config32(dev, dev->link[link].cap + 0x18);
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} while(!(link_type & InitComplete));
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if (!(link_type & NonCoherent)) {
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return max;
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}
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/* See if there is an available configuration space mapping
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* register in function 1.
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*/
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free_reg = 0;
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for(config_reg = 0xe0; config_reg <= 0xec; config_reg += 4) {
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u32 config;
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config = f1_read_config32(config_reg);
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if (!free_reg && ((config & 3) == 0)) {
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free_reg = config_reg;
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continue;
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}
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if (((config & 3) == 3) &&
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(((config >> 4) & 7) == nodeid) &&
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(((config >> 8) & 3) == link)) {
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break;
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}
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}
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if (free_reg && (config_reg > 0xec)) {
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config_reg = free_reg;
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}
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/* If we can't find an available configuration space mapping
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* register skip this bus
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*/
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if (config_reg > 0xec) {
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return max;
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if (((config & 3) == 3) &&
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(((config >> 4) & 7) == nodeid) &&
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(((config >> 8) & 3) == link)) {
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break;
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}
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}
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if (free_reg && (config_reg > 0xec)) {
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config_reg = free_reg;
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}
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/* If we can't find an available configuration space mapping
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* register skip this bus
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*/
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if (config_reg > 0xec) {
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return max;
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}
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/* Set up the primary, secondary and subordinate bus numbers.
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* We have no idea how many busses are behind this bridge yet,
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* so we set the subordinate bus number to 0xff for the moment.
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*/
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/* Set up the primary, secondary and subordinate bus numbers.
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* We have no idea how many busses are behind this bridge yet,
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* so we set the subordinate bus number to 0xff for the moment.
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*/
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#if SB_HT_CHAIN_ON_BUS0 > 0
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// first chain will on bus 0
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if((nodeid == 0) && (sblink==link)) { // actually max is 0 here
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min_bus = max;
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}
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// first chain will on bus 0
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if ((nodeid == 0) && (sblink == link)) { // actually max is 0 here
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min_bus = max;
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}
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#if SB_HT_CHAIN_ON_BUS0 > 1
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// second chain will be on 0x40, third 0x80, forth 0xc0
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else {
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min_bus = ((max>>6) + 1) * 0x40;
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}
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max = min_bus;
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// second chain will be on 0x40, third 0x80, forth 0xc0
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else {
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min_bus = ((max >> 6) + 1) * 0x40;
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}
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max = min_bus;
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#else
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//other ...
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else {
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min_bus = ++max;
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}
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//other ...
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else {
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min_bus = ++max;
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}
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#endif
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#else
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min_bus = ++max;
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min_bus = ++max;
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#endif
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max_bus = 0xff;
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max_bus = 0xff;
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dev->link[link].secondary = min_bus;
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dev->link[link].subordinate = max_bus;
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dev->link[link].secondary = min_bus;
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dev->link[link].subordinate = max_bus;
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/* Read the existing primary/secondary/subordinate bus
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* number configuration.
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*/
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busses = pci_read_config32(dev, dev->link[link].cap + 0x14);
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config_busses = f1_read_config32(config_reg);
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/* Read the existing primary/secondary/subordinate bus
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* number configuration.
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*/
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busses = pci_read_config32(dev, dev->link[link].cap + 0x14);
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config_busses = f1_read_config32(config_reg);
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/* Configure the bus numbers for this bridge: the configuration
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* transactions will not be propagates by the bridge if it is
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* not correctly configured
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*/
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busses &= 0xff000000;
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busses |= (((unsigned int)(dev->bus->secondary) << 0) |
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((unsigned int)(dev->link[link].secondary) << 8) |
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((unsigned int)(dev->link[link].subordinate) << 16));
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pci_write_config32(dev, dev->link[link].cap + 0x14, busses);
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/* Configure the bus numbers for this bridge: the configuration
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* transactions will not be propagates by the bridge if it is
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* not correctly configured
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*/
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busses &= 0xff000000;
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busses |= (((unsigned int)(dev->bus->secondary) << 0) |
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((unsigned int)(dev->link[link].secondary) << 8) |
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((unsigned int)(dev->link[link].subordinate) << 16));
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pci_write_config32(dev, dev->link[link].cap + 0x14, busses);
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config_busses &= 0x000fc88;
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config_busses |=
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(3 << 0) | /* rw enable, no device compare */
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(( nodeid & 7) << 4) |
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(( link & 3 ) << 8) |
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((dev->link[link].secondary) << 16) |
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((dev->link[link].subordinate) << 24);
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f1_write_config32(config_reg, config_busses);
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config_busses &= 0x000fc88;
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config_busses |= (3 << 0) | /* rw enable, no device compare */
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((nodeid & 7) << 4) |
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((link & 3) << 8) |
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((dev->link[link].secondary) << 16) |
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((dev->link[link].subordinate) << 24);
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f1_write_config32(config_reg, config_busses);
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/* Now we can scan all of the subordinate busses i.e. the
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* chain on the hypertranport link
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*/
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for(i=0;i<4;i++) {
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ht_unitid_base[i] = 0x20;
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/* Now we can scan all of the subordinate busses i.e. the
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* chain on the hypertranport link
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*/
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for (i = 0; i < 4; i++) {
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ht_unitid_base[i] = 0x20;
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}
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if (min_bus == 0)
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max_devfn = (0x17 << 3) | 7;
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else
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max_devfn = (0x1f << 3) | 7;
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max =
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hypertransport_scan_chain(&dev->link[link], 0, max_devfn, max,
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ht_unitid_base, offset_unitid);
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/* We know the number of busses behind this bridge. Set the
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* subordinate bus number to it's real value
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*/
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dev->link[link].subordinate = max;
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busses = (busses & 0xff00ffff) |
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((unsigned int)(dev->link[link].subordinate) << 16);
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pci_write_config32(dev, dev->link[link].cap + 0x14, busses);
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config_busses = (config_busses & 0x00ffffff) |
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(dev->link[link].subordinate << 24);
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f1_write_config32(config_reg, config_busses);
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{
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// config config_reg, and ht_unitid_base to update hcdn_reg;
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int index;
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unsigned temp = 0;
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index = (config_reg - 0xe0) >> 2;
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for (i = 0; i < 4; i++) {
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temp |= (ht_unitid_base[i] & 0xff) << (i * 8);
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}
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if (min_bus == 0)
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max_devfn = (0x17<<3) | 7;
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else
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max_devfn = (0x1f<<3) | 7;
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sysconf.hcdn_reg[index] = temp;
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max = hypertransport_scan_chain(&dev->link[link], 0, max_devfn, max, ht_unitid_base, offset_unitid);
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/* We know the number of busses behind this bridge. Set the
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* subordinate bus number to it's real value
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*/
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dev->link[link].subordinate = max;
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busses = (busses & 0xff00ffff) |
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((unsigned int) (dev->link[link].subordinate) << 16);
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pci_write_config32(dev, dev->link[link].cap + 0x14, busses);
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config_busses = (config_busses & 0x00ffffff) |
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(dev->link[link].subordinate << 24);
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f1_write_config32(config_reg, config_busses);
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{
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// config config_reg, and ht_unitid_base to update hcdn_reg;
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int index;
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unsigned temp = 0;
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index = (config_reg-0xe0) >> 2;
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for(i=0;i<4;i++) {
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temp |= (ht_unitid_base[i] & 0xff) << (i*8);
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}
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sysconf.hcdn_reg[index] = temp;
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}
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}
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printk(BIOS_SPEW, "amdk8_scan_chain done\n");
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return max;
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}
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static unsigned int amdk8_scan_chains(struct device * dev, unsigned int max)
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static unsigned int amdk8_scan_chains(struct device *dev, unsigned int max)
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{
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unsigned nodeid;
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unsigned link;
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@ -213,31 +216,35 @@ static unsigned int amdk8_scan_chains(struct device * dev, unsigned int max)
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printk(BIOS_DEBUG, "amdk8_scan_chains\n");
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if(nodeid==0) {
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sblink = (pci_read_config32(dev, 0x64)>>8) & 3;
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if (nodeid == 0) {
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sblink = (pci_read_config32(dev, 0x64) >> 8) & 3;
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#if SB_HT_CHAIN_ON_BUS0 > 0
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#if ((HT_CHAIN_UNITID_BASE != 1) || (HT_CHAIN_END_UNITID_BASE != 0x20))
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#if ((HT_CHAIN_UNITID_BASE != 1) || (HT_CHAIN_END_UNITID_BASE != 0x20))
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offset_unitid = 1;
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#endif
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#endif
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// do southbridge ht chain first, in case s2885 put southbridge chain (8131/8111) on link2,
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// but put 8151 on link0
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max = amdk8_scan_chain(dev, nodeid, sblink, sblink, max, offset_unitid );
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max =
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amdk8_scan_chain(dev, nodeid, sblink, sblink, max,
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offset_unitid);
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#endif
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}
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for(link = 0; link < dev->links; link++) {
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for (link = 0; link < dev->links; link++) {
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#if SB_HT_CHAIN_ON_BUS0 > 0
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if( (nodeid == 0) && (sblink == link) ) continue; //already done
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if ((nodeid == 0) && (sblink == link))
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continue; //already done
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#endif
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offset_unitid = 0;
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#if ((HT_CHAIN_UNITID_BASE != 1) || (HT_CHAIN_END_UNITID_BASE != 0x20))
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#if SB_HT_CHAIN_UNITID_OFFSET_ONLY == 1
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if((nodeid == 0) && (sblink == link))
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#endif
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offset_unitid = 1;
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#endif
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#if ((HT_CHAIN_UNITID_BASE != 1) || (HT_CHAIN_END_UNITID_BASE != 0x20))
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#if SB_HT_CHAIN_UNITID_OFFSET_ONLY == 1
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if ((nodeid == 0) && (sblink == link))
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#endif
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offset_unitid = 1;
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#endif
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max = amdk8_scan_chain(dev, nodeid, link, sblink, max, offset_unitid);
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max = amdk8_scan_chain(dev, nodeid, link, sblink, max,
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offset_unitid);
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}
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return max;
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@ -253,32 +260,32 @@ static unsigned int amdk8_scan_chains(struct device * dev, unsigned int max)
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* __f0 is initialized once in amdk8_read_resources
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*/
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static int reg_useable(unsigned reg,
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struct device * goal_dev, unsigned goal_nodeid, unsigned goal_link)
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struct device *goal_dev, unsigned goal_nodeid,
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unsigned goal_link)
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{
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struct resource *res;
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unsigned nodeid, link=0;
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unsigned nodeid, link = 0;
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int result;
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res = NULL;
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/* Look for the resource that matches this register. */
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for(nodeid = 0; !res && (nodeid < CONFIG_MAX_PHYSICAL_CPUS); nodeid++) {
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struct device * dev;
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for (nodeid = 0; !res && (nodeid < CONFIG_MAX_PHYSICAL_CPUS); nodeid++) {
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struct device *dev;
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dev = __f0_dev[nodeid];
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if (! dev)
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if (!dev)
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continue;
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for(link = 0; !res && (link < 3); link++) {
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for (link = 0; !res && (link < 3); link++) {
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res = probe_resource(dev, 0x100 + (reg | link));
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}
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}
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/* If no allocated resource was found, it is free - return 2 */
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result = 2;
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if (res) {
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result = 0;
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/* If the resource is allocated to the link and node already */
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if ( (goal_link == (link - 1)) &&
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(goal_nodeid == (nodeid - 1)) &&
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(res->flags <= 1)) {
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if ((goal_link == (link - 1)) &&
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(goal_nodeid == (nodeid - 1)) && (res->flags <= 1)) {
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result = 1;
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}
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}
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@ -286,20 +293,20 @@ static int reg_useable(unsigned reg,
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return result;
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}
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static struct resource *amdk8_find_iopair(struct device * dev, unsigned nodeid, unsigned link)
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static struct resource *amdk8_find_iopair(struct device *dev, unsigned nodeid,
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unsigned link)
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{
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struct resource *resource;
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unsigned free_reg, reg;
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resource = NULL;
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free_reg = 0;
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for(reg = 0xc0; reg <= 0xd8; reg += 0x8) {
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for (reg = 0xc0; reg <= 0xd8; reg += 0x8) {
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int result;
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result = reg_useable(reg, dev, nodeid, link);
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if (result == 1) {
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/* I have been allocated this one */
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break;
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}
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else if (result > 1) {
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} else if (result > 1) {
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/* I have a free register pair */
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free_reg = reg;
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}
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@ -313,20 +320,20 @@ static struct resource *amdk8_find_iopair(struct device * dev, unsigned nodeid,
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return resource;
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}
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static struct resource *amdk8_find_mempair(struct device * dev, unsigned nodeid, unsigned link)
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static struct resource *amdk8_find_mempair(struct device *dev, unsigned nodeid,
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unsigned link)
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{
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struct resource *resource;
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unsigned free_reg, reg;
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resource = NULL;
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free_reg = 0;
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for(reg = 0x80; reg <= 0xb8; reg += 0x8) {
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for (reg = 0x80; reg <= 0xb8; reg += 0x8) {
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int result;
|
||||
result = reg_useable(reg, dev, nodeid, link);
|
||||
if (result == 1) {
|
||||
/* I have been allocated this one */
|
||||
break;
|
||||
}
|
||||
else if (result > 1) {
|
||||
} else if (result > 1) {
|
||||
/* I have a free register pair */
|
||||
free_reg = reg;
|
||||
}
|
||||
|
|
@ -340,70 +347,73 @@ static struct resource *amdk8_find_mempair(struct device * dev, unsigned nodeid,
|
|||
return resource;
|
||||
}
|
||||
|
||||
static void amdk8_link_read_bases(struct device * dev, unsigned nodeid, unsigned link)
|
||||
static void amdk8_link_read_bases(struct device *dev, unsigned nodeid,
|
||||
unsigned link)
|
||||
{
|
||||
struct resource *resource;
|
||||
|
||||
/* Initialize the io space constraints on the current bus */
|
||||
resource = amdk8_find_iopair(dev, nodeid, link);
|
||||
resource = amdk8_find_iopair(dev, nodeid, link);
|
||||
if (resource) {
|
||||
resource->base = 0;
|
||||
resource->size = 0;
|
||||
resource->base = 0;
|
||||
resource->size = 0;
|
||||
resource->align = log2c(HT_IO_HOST_ALIGN);
|
||||
resource->gran = log2c(HT_IO_HOST_ALIGN);
|
||||
resource->gran = log2c(HT_IO_HOST_ALIGN);
|
||||
resource->limit = 0xffffUL;
|
||||
resource->flags = IORESOURCE_IO;
|
||||
compute_allocate_resource(&dev->link[link], resource,
|
||||
IORESOURCE_IO, IORESOURCE_IO);
|
||||
IORESOURCE_IO, IORESOURCE_IO);
|
||||
}
|
||||
|
||||
/* Initialize the prefetchable memory constraints on the current bus */
|
||||
resource = amdk8_find_mempair(dev, nodeid, link);
|
||||
if (resource) {
|
||||
resource->base = 0;
|
||||
resource->size = 0;
|
||||
resource->base = 0;
|
||||
resource->size = 0;
|
||||
resource->align = log2c(HT_MEM_HOST_ALIGN);
|
||||
resource->gran = log2c(HT_MEM_HOST_ALIGN);
|
||||
resource->gran = log2c(HT_MEM_HOST_ALIGN);
|
||||
resource->limit = 0xffffffffffULL;
|
||||
resource->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH;
|
||||
compute_allocate_resource(&dev->link[link], resource,
|
||||
IORESOURCE_MEM | IORESOURCE_PREFETCH,
|
||||
IORESOURCE_MEM | IORESOURCE_PREFETCH);
|
||||
IORESOURCE_MEM | IORESOURCE_PREFETCH,
|
||||
IORESOURCE_MEM | IORESOURCE_PREFETCH);
|
||||
}
|
||||
|
||||
/* Initialize the memory constraints on the current bus */
|
||||
resource = amdk8_find_mempair(dev, nodeid, link);
|
||||
if (resource) {
|
||||
resource->base = 0;
|
||||
resource->size = 0;
|
||||
resource->base = 0;
|
||||
resource->size = 0;
|
||||
resource->align = log2c(HT_MEM_HOST_ALIGN);
|
||||
resource->gran = log2c(HT_MEM_HOST_ALIGN);
|
||||
resource->gran = log2c(HT_MEM_HOST_ALIGN);
|
||||
resource->limit = 0xffffffffffULL;
|
||||
resource->flags = IORESOURCE_MEM;
|
||||
compute_allocate_resource(&dev->link[link], resource,
|
||||
IORESOURCE_MEM | IORESOURCE_PREFETCH,
|
||||
IORESOURCE_MEM);
|
||||
IORESOURCE_MEM | IORESOURCE_PREFETCH,
|
||||
IORESOURCE_MEM);
|
||||
}
|
||||
}
|
||||
|
||||
static void amdk8_read_resources(struct device * dev)
|
||||
static void amdk8_read_resources(struct device *dev)
|
||||
{
|
||||
printk(BIOS_DEBUG, "amdk8_read_resources\n");
|
||||
unsigned nodeid, link;
|
||||
nodeid = amdk8_nodeid(dev);
|
||||
|
||||
get_fx_devs(); /* Make sure __f0 is initialized*/
|
||||
get_fx_devs(); /* Make sure __f0 is initialized */
|
||||
|
||||
for(link = 0; link < dev->links; link++) {
|
||||
for (link = 0; link < dev->links; link++) {
|
||||
if (dev->link[link].children) {
|
||||
printk(BIOS_DEBUG, "amdk8_read_resources link %d\n", link);
|
||||
printk(BIOS_DEBUG, "amdk8_read_resources link %d\n",
|
||||
link);
|
||||
amdk8_link_read_bases(dev, nodeid, link);
|
||||
}
|
||||
}
|
||||
printk(BIOS_DEBUG, "amdk8_read_resources done\n");
|
||||
}
|
||||
|
||||
static void amdk8_set_resource(struct device * dev, struct resource *resource, unsigned nodeid)
|
||||
static void amdk8_set_resource(struct device *dev, struct resource *resource,
|
||||
unsigned nodeid)
|
||||
{
|
||||
resource_t rbase, rend;
|
||||
unsigned reg, link;
|
||||
|
|
@ -431,29 +441,30 @@ static void amdk8_set_resource(struct device * dev, struct resource *resource, u
|
|||
rbase = resource->base;
|
||||
|
||||
/* Get the limit (rounded up) */
|
||||
rend = resource_end(resource);
|
||||
rend = resource_end(resource);
|
||||
|
||||
/* Get the register and link */
|
||||
reg = resource->index & 0xfc;
|
||||
reg = resource->index & 0xfc;
|
||||
link = resource->index & 3;
|
||||
|
||||
if (resource->flags & IORESOURCE_IO) {
|
||||
u32 base, limit;
|
||||
compute_allocate_resource(&dev->link[link], resource,
|
||||
IORESOURCE_IO, IORESOURCE_IO);
|
||||
base = f1_read_config32(reg);
|
||||
IORESOURCE_IO, IORESOURCE_IO);
|
||||
base = f1_read_config32(reg);
|
||||
limit = f1_read_config32(reg + 0x4);
|
||||
base &= 0xfe000fcc;
|
||||
base |= rbase & 0x01fff000;
|
||||
base |= 3;
|
||||
base &= 0xfe000fcc;
|
||||
base |= rbase & 0x01fff000;
|
||||
base |= 3;
|
||||
limit &= 0xfe000fc8;
|
||||
limit |= rend & 0x01fff000;
|
||||
limit |= (link & 3) << 4;
|
||||
limit |= (nodeid & 7);
|
||||
|
||||
if (dev->link[link].bridge_ctrl & PCI_BRIDGE_CTL_VGA) {
|
||||
printk(BIOS_SPEW, "%s, enabling legacy VGA IO forwarding for %s link %x\n",
|
||||
__func__, dev_path(dev), link);
|
||||
printk(BIOS_SPEW,
|
||||
"%s, enabling legacy VGA IO forwarding for %s link %x\n",
|
||||
__func__, dev_path(dev), link);
|
||||
base |= PCI_IO_BASE_VGA_EN;
|
||||
}
|
||||
if (dev->link[link].bridge_ctrl & PCI_BRIDGE_CTL_NO_ISA) {
|
||||
|
|
@ -462,17 +473,18 @@ static void amdk8_set_resource(struct device * dev, struct resource *resource, u
|
|||
|
||||
f1_write_config32(reg + 0x4, limit);
|
||||
f1_write_config32(reg, base);
|
||||
}
|
||||
else if (resource->flags & IORESOURCE_MEM) {
|
||||
} else if (resource->flags & IORESOURCE_MEM) {
|
||||
u32 base, limit;
|
||||
compute_allocate_resource(&dev->link[link], resource,
|
||||
IORESOURCE_MEM | IORESOURCE_PREFETCH,
|
||||
resource->flags & (IORESOURCE_MEM | IORESOURCE_PREFETCH));
|
||||
base = f1_read_config32(reg);
|
||||
IORESOURCE_MEM | IORESOURCE_PREFETCH,
|
||||
resource->
|
||||
flags & (IORESOURCE_MEM |
|
||||
IORESOURCE_PREFETCH));
|
||||
base = f1_read_config32(reg);
|
||||
limit = f1_read_config32(reg + 0x4);
|
||||
base &= 0x000000f0;
|
||||
base |= (rbase >> 8) & 0xffffff00;
|
||||
base |= 3;
|
||||
base &= 0x000000f0;
|
||||
base |= (rbase >> 8) & 0xffffff00;
|
||||
base |= 3;
|
||||
limit &= 0x00000048;
|
||||
limit |= (rend >> 8) & 0xffffff00;
|
||||
limit |= (link & 3) << 4;
|
||||
|
|
@ -481,8 +493,7 @@ static void amdk8_set_resource(struct device * dev, struct resource *resource, u
|
|||
f1_write_config32(reg, base);
|
||||
}
|
||||
resource->flags |= IORESOURCE_STORED;
|
||||
sprintf(buf, " <node %d link %d>",
|
||||
nodeid, link);
|
||||
sprintf(buf, " <node %d link %d>", nodeid, link);
|
||||
report_resource_stored(dev, resource, buf);
|
||||
}
|
||||
|
||||
|
|
@ -492,10 +503,10 @@ static void amdk8_set_resource(struct device * dev, struct resource *resource, u
|
|||
* but it is too diffcult to deal with the resource allocation magic.
|
||||
*/
|
||||
#ifdef CONFIG_MULTIPLE_VGA_INIT
|
||||
extern struct device * vga_pri; // the primary vga device, defined in device.c
|
||||
extern struct device *vga_pri; // the primary vga device, defined in device.c
|
||||
#endif
|
||||
|
||||
static void amdk8_create_vga_resource(struct device * dev, unsigned nodeid)
|
||||
static void amdk8_create_vga_resource(struct device *dev, unsigned nodeid)
|
||||
{
|
||||
struct resource *resource;
|
||||
unsigned link;
|
||||
|
|
@ -507,14 +518,19 @@ static void amdk8_create_vga_resource(struct device * dev, unsigned nodeid)
|
|||
for (link = 0; link < dev->links; link++) {
|
||||
if (dev->link[link].bridge_ctrl & PCI_BRIDGE_CTL_VGA) {
|
||||
#ifdef CONFIG_MULTIPLE_VGA_INIT
|
||||
printk(BIOS_DEBUG, "VGA: vga_pri bus num = %d dev->link[link] bus range [%d,%d]\n", vga_pri->bus->secondary,
|
||||
dev->link[link].secondary,dev->link[link].subordinate);
|
||||
printk(BIOS_DEBUG,
|
||||
"VGA: vga_pri bus num = %d dev->link[link] bus range [%d,%d]\n",
|
||||
vga_pri->bus->secondary,
|
||||
dev->link[link].secondary,
|
||||
dev->link[link].subordinate);
|
||||
/* We need to make sure the vga_pri is under the link */
|
||||
if((vga_pri->bus->secondary >= dev->link[link].secondary ) &&
|
||||
(vga_pri->bus->secondary <= dev->link[link].subordinate )
|
||||
)
|
||||
if ((vga_pri->bus->secondary >=
|
||||
dev->link[link].secondary)
|
||||
&& (vga_pri->bus->secondary <=
|
||||
dev->link[link].subordinate)
|
||||
)
|
||||
#endif
|
||||
break;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -522,24 +538,26 @@ static void amdk8_create_vga_resource(struct device * dev, unsigned nodeid)
|
|||
if (link == dev->links)
|
||||
return;
|
||||
|
||||
printk(BIOS_DEBUG, "VGA: %s (aka node %d) link %d has VGA device\n", dev_path(dev), nodeid, link);
|
||||
printk(BIOS_DEBUG, "VGA: %s (aka node %d) link %d has VGA device\n",
|
||||
dev_path(dev), nodeid, link);
|
||||
|
||||
/* allocate a temp resrouce for legacy VGA buffer */
|
||||
resource = amdk8_find_mempair(dev, nodeid, link);
|
||||
if(!resource){
|
||||
printk(BIOS_DEBUG, "VGA: Can not find free mmio reg for legacy VGA buffer\n");
|
||||
if (!resource) {
|
||||
printk(BIOS_DEBUG,
|
||||
"VGA: Can not find free mmio reg for legacy VGA buffer\n");
|
||||
return;
|
||||
}
|
||||
resource->base = 0xa0000;
|
||||
resource->size = 0x20000;
|
||||
|
||||
/* write the resource to the hardware */
|
||||
reg = resource->index & 0xfc;
|
||||
base = f1_read_config32(reg);
|
||||
reg = resource->index & 0xfc;
|
||||
base = f1_read_config32(reg);
|
||||
limit = f1_read_config32(reg + 0x4);
|
||||
base &= 0x000000f0;
|
||||
base |= (resource->base >> 8) & 0xffffff00;
|
||||
base |= 3;
|
||||
base &= 0x000000f0;
|
||||
base |= (resource->base >> 8) & 0xffffff00;
|
||||
base |= 3;
|
||||
limit &= 0x00000048;
|
||||
limit |= (resource_end(resource) >> 8) & 0xffffff00;
|
||||
limit |= (resource->index & 3) << 4;
|
||||
|
|
@ -551,7 +569,7 @@ static void amdk8_create_vga_resource(struct device * dev, unsigned nodeid)
|
|||
resource->flags = 0;
|
||||
}
|
||||
|
||||
static void amdk8_set_resources(struct device * dev)
|
||||
static void amdk8_set_resources(struct device *dev)
|
||||
{
|
||||
unsigned nodeid, link;
|
||||
int i;
|
||||
|
|
@ -563,11 +581,11 @@ static void amdk8_set_resources(struct device * dev)
|
|||
amdk8_create_vga_resource(dev, nodeid);
|
||||
|
||||
/* Set each resource we have found */
|
||||
for(i = 0; i < dev->resources; i++) {
|
||||
for (i = 0; i < dev->resources; i++) {
|
||||
amdk8_set_resource(dev, &dev->resource[i], nodeid);
|
||||
}
|
||||
|
||||
for(link = 0; link < dev->links; link++) {
|
||||
for (link = 0; link < dev->links; link++) {
|
||||
struct bus *bus;
|
||||
bus = &dev->link[link];
|
||||
if (bus->children) {
|
||||
|
|
@ -576,7 +594,7 @@ static void amdk8_set_resources(struct device * dev)
|
|||
}
|
||||
}
|
||||
|
||||
static void amdk8_enable_resources(struct device * dev)
|
||||
static void amdk8_enable_resources(struct device *dev)
|
||||
{
|
||||
printk(BIOS_DEBUG, "amdk8_enable_resources\n");
|
||||
pci_dev_enable_resources(dev);
|
||||
|
|
@ -596,8 +614,8 @@ static void mcf0_control_init(struct device *dev)
|
|||
|
||||
struct device_operations k8_ops = {
|
||||
.id = {.type = DEVICE_ID_PCI,
|
||||
{.pci = {.vendor = PCI_VENDOR_ID_AMD,
|
||||
.device = 0x1100}}},
|
||||
{.pci = {.vendor = PCI_VENDOR_ID_AMD,
|
||||
.device = 0x1100}}},
|
||||
.constructor = default_device_constructor,
|
||||
.reset_bus = pci_bus_reset,
|
||||
.phase3_scan = amdk8_scan_chains,
|
||||
|
|
@ -606,5 +624,5 @@ struct device_operations k8_ops = {
|
|||
.phase5_enable_resources = amdk8_enable_resources,
|
||||
.phase6_init = mcf0_control_init,
|
||||
.ops_pci = &pci_dev_ops_pci,
|
||||
.ops_pci_bus = &pci_cf8_conf1,
|
||||
.ops_pci_bus = &pci_cf8_conf1,
|
||||
};
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue