Fixed whitespace and indentation

Code style fixes for the hp/dl145_g1 system board code.

Change-Id: I3c1a175d954e2d340e82c03c9f984699dcff865e
Signed-off-by: Oskar Enoksson <enok@lysator.liu.se>
Reviewed-on: http://review.coreboot.org/428
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This commit is contained in:
Oskar Enoksson 2011-11-07 18:31:33 +01:00 committed by Stefan Reinauer
parent c1a75b13c3
commit f5e102d810
6 changed files with 284 additions and 284 deletions

View file

@ -1,142 +1,142 @@
chip northbridge/amd/amdk8/root_complex chip northbridge/amd/amdk8/root_complex
device lapic_cluster 0 on device lapic_cluster 0 on
chip cpu/amd/socket_940 chip cpu/amd/socket_940
device lapic 0 on end device lapic 0 on end
end end
end end
device pci_domain 0 on device pci_domain 0 on
subsystemid 0x1022 0x7460 inherit subsystemid 0x1022 0x7460 inherit
chip northbridge/amd/amdk8 chip northbridge/amd/amdk8
device pci 18.0 on end # link 0 device pci 18.0 on end # link 0
device pci 18.0 on end # link 1 device pci 18.0 on end # link 1
device pci 18.0 on # link 2 device pci 18.0 on # link 2
chip southbridge/amd/amd8131 chip southbridge/amd/amd8131
# the on/off keyword is mandatory # the on/off keyword is mandatory
device pci 0.0 on # PCIX Bridge A device pci 0.0 on # PCIX Bridge A
# PCI-X expansion slot cards auto-detected here # PCI-X expansion slot cards auto-detected here
end end
device pci 0.1 on end # IOAPIC A device pci 0.1 on end # IOAPIC A
device pci 1.0 on # PCIX Bridge B device pci 1.0 on # PCIX Bridge B
# On-board BCM5704 dual port ethernet chip auto-detected here # On-board BCM5704 dual port ethernet chip auto-detected here
# Optional SCSI board also (?) # Optional SCSI board also (?)
end end
device pci 1.1 on end # IOAPIC B device pci 1.1 on end # IOAPIC B
device pci 2.0 off end device pci 2.0 off end
end end
chip southbridge/amd/amd8111 chip southbridge/amd/amd8111
# this "device pci 0.0" is the parent of the next one # this "device pci 0.0" is the parent of the next one
# PCI bridge # PCI bridge
device pci 0.0 on device pci 0.0 on
device pci 0.0 on end # OHCI-based USB controller 0 device pci 0.0 on end # OHCI-based USB controller 0
device pci 0.1 on end # OCHI-based USB controller 1 device pci 0.1 on end # OCHI-based USB controller 1
device pci 0.2 on end # EHCI-based USB2 controller device pci 0.2 on end # EHCI-based USB2 controller
device pci 1.0 off end # LAN Ethernet controller device pci 1.0 off end # LAN Ethernet controller
#device pci 4.0 on end # VGA PCI-card (auto detected) #device pci 4.0 on end # VGA PCI-card (auto detected)
end end
device pci 1.0 on # LPC Bridge device pci 1.0 on # LPC Bridge
chip superio/winbond/w83627hf chip superio/winbond/w83627hf
device pnp 2e.0 off # Floppy device pnp 2e.0 off # Floppy
#io 0x60 = 0x3f0 #io 0x60 = 0x3f0
#irq 0x70 = 6 #irq 0x70 = 6
#drq 0x74 = 2 #drq 0x74 = 2
end end
device pnp 2e.1 off # Parallel Port device pnp 2e.1 off # Parallel Port
#io 0x60 = 0x378 #io 0x60 = 0x378
#irq 0x70 = 7 #irq 0x70 = 7
#drq 0x74 = 1 #drq 0x74 = 1
end end
device pnp 2e.2 on # Com1 device pnp 2e.2 on # Com1
io 0x60 = 0x3f8 io 0x60 = 0x3f8
irq 0x70 = 4 irq 0x70 = 4
end end
device pnp 2e.3 off # Com2 device pnp 2e.3 off # Com2
#io 0x60 = 0x2f8 #io 0x60 = 0x2f8
#irq 0x70 = 3 #irq 0x70 = 3
end end
device pnp 2e.5 on # Keyboard device pnp 2e.5 on # Keyboard
io 0x60 = 0x60 io 0x60 = 0x60
io 0x62 = 0x64 io 0x62 = 0x64
irq 0x70 = 1 irq 0x70 = 1
irq 0x72 = 12 irq 0x72 = 12
end end
device pnp 2e.6 off # CIR device pnp 2e.6 off # CIR
end end
device pnp 2e.7 off # GAM_MIDI_GPIO1 device pnp 2e.7 off # GAM_MIDI_GPIO1
#io 0x60 = 0x201 #io 0x60 = 0x201
#io 0x62 = 0x330 #io 0x62 = 0x330
#irq 0x70 = 9 #irq 0x70 = 9
end end
device pnp 2e.8 on # GPIO2 (watchdog timer) device pnp 2e.8 on # GPIO2 (watchdog timer)
end end
device pnp 2e.9 on # GPIO3 device pnp 2e.9 on # GPIO3
end end
device pnp 2e.a on # ACPI device pnp 2e.a on # ACPI
end end
device pnp 2e.b on # HW Monitor device pnp 2e.b on # HW Monitor
io 0x60 = 0x290 io 0x60 = 0x290
irq 0x70 = 5 irq 0x70 = 5
end end
end end
end end
device pci 1.1 on end # EIDE controller device pci 1.1 on end # EIDE controller
device pci 1.2 on device pci 1.2 on
chip drivers/generic/generic chip drivers/generic/generic
device i2c 8 on end # Some HW-monitor/sensor? device i2c 8 on end # Some HW-monitor/sensor?
end end
end end
device pci 1.2 on device pci 1.2 on
chip drivers/i2c/i2cmux # Multplexed DIMM spd eeproms. chip drivers/i2c/i2cmux # Multplexed DIMM spd eeproms.
device i2c 18 on #0 pca9516 (?) device i2c 18 on #0 pca9516 (?)
# Some dimms also listen to address 30-33 # Some dimms also listen to address 30-33
# It's some kind of write-protect function # It's some kind of write-protect function
# The 50-53 addresses are the interesting ones. # The 50-53 addresses are the interesting ones.
chip drivers/generic/generic #dimm H0-0 chip drivers/generic/generic #dimm H0-0
device i2c 50 on end device i2c 50 on end
end end
chip drivers/generic/generic #dimm H0-1 chip drivers/generic/generic #dimm H0-1
device i2c 51 on end device i2c 51 on end
end end
chip drivers/generic/generic #dimm H0-2 chip drivers/generic/generic #dimm H0-2
device i2c 52 on end device i2c 52 on end
end end
chip drivers/generic/generic #dimm H0-3 chip drivers/generic/generic #dimm H0-3
device i2c 53 on end device i2c 53 on end
end end
end end
device i2c 18 on #1 pca9516 (?) device i2c 18 on #1 pca9516 (?)
chip drivers/generic/generic #dimm H1-0 chip drivers/generic/generic #dimm H1-0
device i2c 50 on end device i2c 50 on end
end end
chip drivers/generic/generic #dimm H1-1 chip drivers/generic/generic #dimm H1-1
device i2c 51 on end device i2c 51 on end
end end
chip drivers/generic/generic #dimm H1-2 chip drivers/generic/generic #dimm H1-2
device i2c 52 on end device i2c 52 on end
end end
chip drivers/generic/generic #dimm H1-3 chip drivers/generic/generic #dimm H1-3
device i2c 53 on end device i2c 53 on end
end end
end end
end end
end end
device pci 1.2 on device pci 1.2 on
chip drivers/generic/generic chip drivers/generic/generic
device i2c 69 on end # Texas Instruments cdc960 clock synthesizer device i2c 69 on end # Texas Instruments cdc960 clock synthesizer
end end
end # SMBus 2.0 controller end # SMBus 2.0 controller
device pci 1.3 on # System management registers (ACPI) device pci 1.3 on # System management registers (ACPI)
end # System management end # System management
#device pci 1.4 off end #device pci 1.4 off end
device pci 1.5 off end # AC97 Audio device pci 1.5 off end # AC97 Audio
device pci 1.6 off end # AC97 Modem device pci 1.6 off end # AC97 Modem
register "ide0_enable" = "1" register "ide0_enable" = "1"
register "ide1_enable" = "1" register "ide1_enable" = "1"
end end
end # device pci 18.0 end # device pci 18.0
device pci 18.1 on end device pci 18.1 on end
device pci 18.2 on end device pci 18.2 on end
device pci 18.3 on end device pci 18.3 on end
end end
end end
end end

View file

@ -16,27 +16,27 @@
struct mb_sysconf_t mb_sysconf; struct mb_sysconf_t mb_sysconf;
static unsigned pci1234x[] = static unsigned pci1234x[] =
{ //Here you only need to set value in pci1234 for HT-IO that could be installed or not { //Here you only need to set value in pci1234 for HT-IO that could be installed or not
//You may need to preset pci1234 for HTIO board, please refer to src/northbridge/amd/amdk8/get_sblk_pci1234.c for detail //You may need to preset pci1234 for HTIO board, please refer to src/northbridge/amd/amdk8/get_sblk_pci1234.c for detail
0x0000ff0, 0x0000ff0,
// 0x0000ff0, // 0x0000ff0,
// 0x0000ff0, // 0x0000ff0,
// 0x0000ff0, // 0x0000ff0,
// 0x0000ff0, // 0x0000ff0,
// 0x0000ff0, // 0x0000ff0,
// 0x0000ff0, // 0x0000ff0,
// 0x0000ff0 // 0x0000ff0
}; };
static unsigned hcdnx[] = static unsigned hcdnx[] =
{ //HT Chain device num, actually it is unit id base of every ht device in chain, assume every chain only have 4 ht device at most { //HT Chain device num, actually it is unit id base of every ht device in chain, assume every chain only have 4 ht device at most
0x20202020, 0x20202020,
// 0x20202020, // 0x20202020,
// 0x20202020, // 0x20202020,
// 0x20202020, // 0x20202020,
// 0x20202020, // 0x20202020,
// 0x20202020, // 0x20202020,
// 0x20202020, // 0x20202020,
// 0x20202020, // 0x20202020,
}; };
@ -47,23 +47,23 @@ void get_bus_conf(void)
unsigned apicid_base; unsigned apicid_base;
device_t dev; device_t dev;
int i; int i;
if(get_bus_conf_done==1) return; //do it only once if(get_bus_conf_done==1) return; //do it only once
get_bus_conf_done = 1; get_bus_conf_done = 1;
sysconf.mb = &mb_sysconf; sysconf.mb = &mb_sysconf;
struct mb_sysconf_t *m = sysconf.mb; struct mb_sysconf_t *m = sysconf.mb;
sysconf.hc_possible_num = ARRAY_SIZE(pci1234x); sysconf.hc_possible_num = ARRAY_SIZE(pci1234x);
for(i=0;i<sysconf.hc_possible_num; i++) { for(i=0;i<sysconf.hc_possible_num; i++) {
sysconf.pci1234[i] = pci1234x[i]; sysconf.pci1234[i] = pci1234x[i];
sysconf.hcdn[i] = hcdnx[i]; sysconf.hcdn[i] = hcdnx[i];
} }
get_sblk_pci1234(); get_sblk_pci1234();
sysconf.sbdn = (sysconf.hcdn[0] >> 8) & 0xff; sysconf.sbdn = (sysconf.hcdn[0] >> 8) & 0xff;
m->sbdn3 = sysconf.hcdn[0] & 0xff; m->sbdn3 = sysconf.hcdn[0] & 0xff;
@ -71,32 +71,32 @@ void get_bus_conf(void)
m->bus_8131_0 = (sysconf.pci1234[0] >> 16) & 0xff; m->bus_8131_0 = (sysconf.pci1234[0] >> 16) & 0xff;
m->bus_8111_0 = m->bus_8131_0; m->bus_8111_0 = m->bus_8131_0;
/* 8111 */ /* 8111 */
dev = dev_find_slot(m->bus_8111_0, PCI_DEVFN(sysconf.sbdn,0)); dev = dev_find_slot(m->bus_8111_0, PCI_DEVFN(sysconf.sbdn,0));
if (dev) { if (dev) {
m->bus_8111_1 = pci_read_config8(dev, PCI_SECONDARY_BUS); m->bus_8111_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
} }
else { else {
printk(BIOS_DEBUG, "ERROR - could not find PCI %02x:03.0, using defaults\n", m->bus_8111_0); printk(BIOS_DEBUG, "ERROR - could not find PCI %02x:03.0, using defaults\n", m->bus_8111_0);
} }
/* 8131-1 */ /* 8131-1 */
dev = dev_find_slot(m->bus_8131_0, PCI_DEVFN(m->sbdn3,0)); dev = dev_find_slot(m->bus_8131_0, PCI_DEVFN(m->sbdn3,0));
if (dev) { if (dev) {
m->bus_8131_1 = pci_read_config8(dev, PCI_SECONDARY_BUS); m->bus_8131_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
} }
else { else {
printk(BIOS_DEBUG, "ERROR - could not find PCI %02x:01.0, using defaults\n", m->bus_8131_0); printk(BIOS_DEBUG, "ERROR - could not find PCI %02x:01.0, using defaults\n", m->bus_8131_0);
} }
/* 8131-2 */ /* 8131-2 */
dev = dev_find_slot(m->bus_8131_0, PCI_DEVFN(m->sbdn3+1,0)); dev = dev_find_slot(m->bus_8131_0, PCI_DEVFN(m->sbdn3+1,0));
if (dev) { if (dev) {
m->bus_8131_2 = pci_read_config8(dev, PCI_SECONDARY_BUS); m->bus_8131_2 = pci_read_config8(dev, PCI_SECONDARY_BUS);
} }
else { else {
printk(BIOS_DEBUG, "ERROR - could not find PCI %02x:02.0, using defaults\n", m->bus_8131_0); printk(BIOS_DEBUG, "ERROR - could not find PCI %02x:02.0, using defaults\n", m->bus_8131_0);
} }
/*I/O APICs: APIC ID Version State Address*/ /*I/O APICs: APIC ID Version State Address*/

View file

@ -17,18 +17,18 @@ static void write_pirq_info(struct irq_info *pirq_info, uint8_t bus, uint8_t dev
uint8_t link1, uint16_t bitmap1, uint8_t link2, uint16_t bitmap2,uint8_t link3, uint16_t bitmap3, uint8_t link1, uint16_t bitmap1, uint8_t link2, uint16_t bitmap2,uint8_t link3, uint16_t bitmap3,
uint8_t slot, uint8_t rfu) uint8_t slot, uint8_t rfu)
{ {
pirq_info->bus = bus; pirq_info->bus = bus;
pirq_info->devfn = devfn; pirq_info->devfn = devfn;
pirq_info->irq[0].link = link0; pirq_info->irq[0].link = link0;
pirq_info->irq[0].bitmap = bitmap0; pirq_info->irq[0].bitmap = bitmap0;
pirq_info->irq[1].link = link1; pirq_info->irq[1].link = link1;
pirq_info->irq[1].bitmap = bitmap1; pirq_info->irq[1].bitmap = bitmap1;
pirq_info->irq[2].link = link2; pirq_info->irq[2].link = link2;
pirq_info->irq[2].bitmap = bitmap2; pirq_info->irq[2].bitmap = bitmap2;
pirq_info->irq[3].link = link3; pirq_info->irq[3].link = link3;
pirq_info->irq[3].bitmap = bitmap3; pirq_info->irq[3].bitmap = bitmap3;
pirq_info->slot = slot; pirq_info->slot = slot;
pirq_info->rfu = rfu; pirq_info->rfu = rfu;
} }
unsigned long write_pirq_routing_table(unsigned long addr) unsigned long write_pirq_routing_table(unsigned long addr)
@ -39,17 +39,17 @@ unsigned long write_pirq_routing_table(unsigned long addr)
uint8_t *v; uint8_t *v;
struct mb_sysconf_t *m = sysconf.mb; struct mb_sysconf_t *m = sysconf.mb;
uint8_t sum=0; uint8_t sum=0;
int i; int i;
get_bus_conf(); // it will find out all bus num and apic that share with mptable.c and mptable.c and acpi_tables.c get_bus_conf(); // it will find out all bus num and apic that share with mptable.c and mptable.c and acpi_tables.c
/* Align the table to be 16 byte aligned. */ /* Align the table to be 16 byte aligned. */
addr += 15; addr += 15;
addr &= ~15; addr &= ~15;
/* This table must be betweeen 0xf0000 & 0x100000 */ /* This table must be betweeen 0xf0000 & 0x100000 */
printk(BIOS_INFO, "Writing IRQ routing tables to 0x%lx...", addr); printk(BIOS_INFO, "Writing IRQ routing tables to 0x%lx...", addr);
pirq = (void *)(addr); pirq = (void *)(addr);
v = (uint8_t *)(addr); v = (uint8_t *)(addr);
@ -75,21 +75,21 @@ unsigned long write_pirq_routing_table(unsigned long addr)
write_pirq_info(pirq_info, m->bus_8111_0, ((sysconf.sbdn+1)<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0); write_pirq_info(pirq_info, m->bus_8111_0, ((sysconf.sbdn+1)<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0);
pirq_info++; slot_num++; pirq_info++; slot_num++;
//pcix bridge //pcix bridge
// write_pirq_info(pirq_info, m->bus_8131_0, (m->sbdn3<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0); // write_pirq_info(pirq_info, m->bus_8131_0, (m->sbdn3<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0);
// pirq_info++; slot_num++; // pirq_info++; slot_num++;
pirq_info++; slot_num++; pirq_info++; slot_num++;
pirq->size = 32 + 16 * slot_num; pirq->size = 32 + 16 * slot_num;
for (i = 0; i < pirq->size; i++) for (i = 0; i < pirq->size; i++)
sum += v[i]; sum += v[i];
sum = pirq->checksum - sum; sum = pirq->checksum - sum;
if (sum != pirq->checksum) { if (sum != pirq->checksum) {
pirq->checksum = sum; pirq->checksum = sum;
} }
printk(BIOS_INFO, "done.\n"); printk(BIOS_INFO, "done.\n");

View file

@ -9,11 +9,11 @@ struct mb_sysconf_t {
unsigned char bus_8111_0; unsigned char bus_8111_0;
unsigned char bus_8111_1; unsigned char bus_8111_1;
unsigned apicid_8111; unsigned apicid_8111;
unsigned apicid_8131_1; unsigned apicid_8131_1;
unsigned apicid_8131_2; unsigned apicid_8131_2;
unsigned sbdn3; unsigned sbdn3;
}; };
#endif #endif

View file

@ -9,14 +9,14 @@
static void *smp_write_config_table(void *v) static void *smp_write_config_table(void *v)
{ {
struct mp_config_table *mc; struct mp_config_table *mc;
int bus_isa; int bus_isa;
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
mptable_init(mc, LAPIC_ADDR); mptable_init(mc, LAPIC_ADDR);
smp_write_processors(mc); smp_write_processors(mc);
get_bus_conf(); get_bus_conf();
@ -26,23 +26,23 @@ static void *smp_write_config_table(void *v)
/*I/O APICs: APIC ID Version State Address*/ /*I/O APICs: APIC ID Version State Address*/
smp_write_ioapic(mc, m->apicid_8111, 0x20, IO_APIC_ADDR); smp_write_ioapic(mc, m->apicid_8111, 0x20, IO_APIC_ADDR);
{ {
device_t dev; device_t dev;
struct resource *res; struct resource *res;
dev = dev_find_slot(m->bus_8131_0, PCI_DEVFN(m->sbdn3,1)); dev = dev_find_slot(m->bus_8131_0, PCI_DEVFN(m->sbdn3,1));
if (dev) { if (dev) {
res = find_resource(dev, PCI_BASE_ADDRESS_0); res = find_resource(dev, PCI_BASE_ADDRESS_0);
if (res) { if (res) {
smp_write_ioapic(mc, m->apicid_8131_1, 0x20, res->base); smp_write_ioapic(mc, m->apicid_8131_1, 0x20, res->base);
} }
} }
dev = dev_find_slot(m->bus_8131_0, PCI_DEVFN(m->sbdn3+1,1)); dev = dev_find_slot(m->bus_8131_0, PCI_DEVFN(m->sbdn3+1,1));
if (dev) { if (dev) {
res = find_resource(dev, PCI_BASE_ADDRESS_0); res = find_resource(dev, PCI_BASE_ADDRESS_0);
if (res) { if (res) {
smp_write_ioapic(mc, m->apicid_8131_2, 0x20, res->base); smp_write_ioapic(mc, m->apicid_8131_2, 0x20, res->base);
} }
} }
} }

View file

@ -23,52 +23,52 @@
static void memreset_setup(void) static void memreset_setup(void)
{ {
if (is_cpu_pre_c0()) { if (is_cpu_pre_c0()) {
/* Set the memreset low. */ /* Set the memreset low. */
outb((1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 16); outb((1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 16);
/* Ensure the BIOS has control of the memory lines. */ /* Ensure the BIOS has control of the memory lines. */
outb((1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 17); outb((1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 17);
} else { } else {
/* Ensure the CPU has control of the memory lines. */ /* Ensure the CPU has control of the memory lines. */
outb((1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 17); outb((1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 17);
} }
} }
static void memreset(int controllers, const struct mem_controller *ctrl) static void memreset(int controllers, const struct mem_controller *ctrl)
{ {
if (is_cpu_pre_c0()) { if (is_cpu_pre_c0()) {
udelay(800); udelay(800);
/* Set memreset high. */ /* Set memreset high. */
outb((1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 16); outb((1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 16);
udelay(90); udelay(90);
} }
} }
#define SMBUS_HUB 0x18 #define SMBUS_HUB 0x18
static inline void activate_spd_rom(const struct mem_controller *ctrl) static inline void activate_spd_rom(const struct mem_controller *ctrl)
{ {
int ret,i; int ret,i;
unsigned device=(ctrl->channel0[0])>>8; unsigned device=(ctrl->channel0[0])>>8;
/* the very first write always get COL_STS=1 and ABRT_STS=1, so try another time*/ /* the very first write always get COL_STS=1 and ABRT_STS=1, so try another time*/
i=2; i=2;
do { do {
ret = smbus_write_byte(SMBUS_HUB, 0x01, device); ret = smbus_write_byte(SMBUS_HUB, 0x01, device);
} while ((ret!=0) && (i-->0)); } while ((ret!=0) && (i-->0));
smbus_write_byte(SMBUS_HUB, 0x03, 0); smbus_write_byte(SMBUS_HUB, 0x03, 0);
} }
static inline void change_i2c_mux(unsigned device) static inline void change_i2c_mux(unsigned device)
{ {
int ret, i; int ret, i;
print_debug("change_i2c_mux i="); print_debug_hex8(device); print_debug("\n"); print_debug("change_i2c_mux i="); print_debug_hex8(device); print_debug("\n");
i=2; i=2;
do { do {
ret = smbus_write_byte(SMBUS_HUB, 0x01, device); ret = smbus_write_byte(SMBUS_HUB, 0x01, device);
print_debug("change_i2c_mux 1 ret="); print_debug_hex32(ret); print_debug("\n"); print_debug("change_i2c_mux 1 ret="); print_debug_hex32(ret); print_debug("\n");
} while ((ret!=0) && (i-->0)); } while ((ret!=0) && (i-->0));
ret = smbus_write_byte(SMBUS_HUB, 0x03, 0); ret = smbus_write_byte(SMBUS_HUB, 0x03, 0);
print_debug("change_i2c_mux 2 ret="); print_debug_hex32(ret); print_debug("\n"); print_debug("change_i2c_mux 2 ret="); print_debug_hex32(ret); print_debug("\n");
} }
static inline int spd_read_byte(unsigned device, unsigned address) static inline int spd_read_byte(unsigned device, unsigned address)
@ -107,16 +107,16 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
int needs_reset = 0; int needs_reset = 0;
unsigned bsp_apicid = 0; unsigned bsp_apicid = 0;
if (bist == 0) if (bist == 0)
bsp_apicid = init_cpus(cpu_init_detectedx,sysinfo); bsp_apicid = init_cpus(cpu_init_detectedx,sysinfo);
w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
console_init(); console_init();
/* Halt if there was a built in self test failure */ /* Halt if there was a built in self test failure */
report_bist_failure(bist); report_bist_failure(bist);
printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1); printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1);
setup_dl145g1_resource_map(); setup_dl145g1_resource_map();
//setup_default_resource_map(); //setup_default_resource_map();
@ -127,12 +127,12 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
setup_coherent_ht_domain(); setup_coherent_ht_domain();
wait_all_core0_started(); wait_all_core0_started();
#if CONFIG_LOGICAL_CPUS==1 #if CONFIG_LOGICAL_CPUS==1
// It is said that we should start core1 after all core0 launched // It is said that we should start core1 after all core0 launched
start_other_cores(); start_other_cores();
wait_all_other_cores_started(bsp_apicid); wait_all_other_cores_started(bsp_apicid);
#endif #endif
ht_setup_chains_x(sysinfo); ht_setup_chains_x(sysinfo);
needs_reset |= optimize_link_coherent_ht(); needs_reset |= optimize_link_coherent_ht();
needs_reset |= optimize_link_incoherent_ht(sysinfo); needs_reset |= optimize_link_incoherent_ht(sysinfo);
@ -156,13 +156,13 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
//dump_spd_registers(&sysinfo->ctrl[1]); //dump_spd_registers(&sysinfo->ctrl[1]);
//dump_smbus_registers(); //dump_smbus_registers();
allow_all_aps_stop(bsp_apicid); allow_all_aps_stop(bsp_apicid);
//It's the time to set ctrl now; //It's the time to set ctrl now;
fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr); fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);
memreset_setup(); memreset_setup();
sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo); sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);
//dump_pci_devices(); //dump_pci_devices();