diff --git a/romimages/RON_VIA_SPD/crt0.S b/romimages/RON_VIA_SPD/crt0.S index 52315035d6..372ba2bcfc 100644 --- a/romimages/RON_VIA_SPD/crt0.S +++ b/romimages/RON_VIA_SPD/crt0.S @@ -1,3 +1,6 @@ +/* + v1.0 02/15/2001: To add "afteram.inc" file after test dram. +*/ /* * $ $ * @@ -52,6 +55,8 @@ CALLSP(ramtest) #endif + +#include /* * Copy data into RAM and clear the BSS. Since these segments * isn't really that big we just copy/clear using bytes, not diff --git a/src/northbridge/via/vt8601/afteram.inc b/src/northbridge/via/vt8601/afteram.inc new file mode 100644 index 0000000000..a641f923a5 --- /dev/null +++ b/src/northbridge/via/vt8601/afteram.inc @@ -0,0 +1,50 @@ +/* + v1.0: 02/15/2001: Program procedure to make workable and stable register settings: + (1) Initial registers: 0x40:0x48, 0x41:0x4d, 0x43:0x44, 0x44:0x04, 0x83:0x02, 0x3e:0x0c + v1.1: 02/15/2001: + (1) Initial registers: To add 0x3e:0x0c + (2) After initial: To add bus0, devfn0 0x84:0xc0 + v1.2: 02/15/2001: + To set 0x13 register to 0xd8 value, thus it won't hang the system if enable graphic aperture(0x88 bit 2). But + I am not sure if it would take effect for graphic device. According to the result, the system won't hang and check + the register setting, that's right, they do set those values except the aperture base(0x13) has been changed to 0x84 + which means the pci configure does the resource allocation. But why it won't start up the monitor??? +*/ + +jmp ptp_afteram_set_registers + +ptp_afteram_table: + .byte 0x40, 0x48 + .byte 0x41, 0x4d + .byte 0x43, 0x44 + .byte 0x44, 0x04 + .byte 0x83, 0x02 + .byte 0x3e, 0x0c + .byte 0x0 /* end of table */ + +ptp_afteram_set_registers: + /* standard x86 loop on table until done code */ + /* assumes that: devfn is 8 (safe on anything we've seen) */ + /* which means addresses are a byte */ + /* address is first, then data */ + movl $ptp_afteram_table, %esi +1: + /* zero out eax. This is a must right here. */ + xor %eax, %eax + movb (%esi), %al + testb %al, %al + jz done_ptp_afteram_set_registers + inc %esi + orl $0x0800, %eax + movb (%esi), %dl + PCI_WRITE_CONFIG_BYTE + inc %esi + jmp 1b + +done_ptp_afteram_set_registers: + CS_WRITE($0x13, $0xd8) + CS_WRITE($0x84, $0xc0) + CS_WRITE($0x80, $0x0f) + CS_WRITE($0x88, $0x02) + intel_chip_post_macro(0x99) + diff --git a/src/northbridge/via/vt8601/northbridge.c b/src/northbridge/via/vt8601/northbridge.c index 3a09eaffdc..62966cc4e3 100644 --- a/src/northbridge/via/vt8601/northbridge.c +++ b/src/northbridge/via/vt8601/northbridge.c @@ -1,5 +1,7 @@ #include #include +#include + unsigned long sizeram() { @@ -7,6 +9,7 @@ unsigned long sizeram() unsigned char bank, mem, prevmem; // fix me later -- there are two more banks at 0x56 and 0x57 unsigned long firstbank = 0x5a, lastbank = 0x5f; + u8 sma_status, sma_size, sma_size_bits; struct pci_dev *pcidev; @@ -15,12 +18,22 @@ unsigned long sizeram() if (! pcidev) return 0; + pci_read_config_byte(pcidev, 0xfb, &sma_status); + sma_size_bits = (sma_status >> 4) & 0x03; + if (sma_size_bits > 3) + sma_size = 0; + else + sma_size = 0x01 << sma_size_bits; + for(totalmem = mem = prevmem = 0, bank = firstbank; bank <= lastbank; bank++) { pci_read_config_byte(pcidev, bank, &mem); - totalmem += (mem - prevmem) * 8 * 1024; + totalmem += (mem - prevmem) * 8; prevmem = mem; } + + totalmem -= sma_size; + totalmem *= 1024; printk("sizeram: returning 0x%x KB\n", totalmem); #if 0 @@ -31,3 +44,24 @@ unsigned long sizeram() #endif return totalmem; } + + +/* +unsigned long sizeram() +{ + return 0; +} +*/ + +#ifdef HAVE_FRAMEBUFFER +void framebuffer_on() +{ + unsigned long devfn; + u16 command; + + devfn = PCI_DEVFN(0, 1); + pcibios_read_config_word(0, devfn, 0x3e, &command); + command |= 0x08; + pcibios_write_config_word(0, devfn, 0x3e, command); +} +#endif diff --git a/src/northbridge/via/vt8601/raminitspd.inc b/src/northbridge/via/vt8601/raminitspd.inc index 3dabadad18..7269d140f6 100644 --- a/src/northbridge/via/vt8601/raminitspd.inc +++ b/src/northbridge/via/vt8601/raminitspd.inc @@ -41,6 +41,11 @@ (1) After SPD, set registers: (1) Second to write and modify: 0x70:0xc0, or 0x71:08-->0x71:88, 0x72:ec, 0x73:0c, 0x74:0x0e, or 0x75:0x80-->0x75:0x81, or 0x76:0x80-->0x76:0xd6, or 0x79:0xf0-->0x79:0xf4, 0x7a:0x01 + v1.5: 02/15/2001: To modify and add: + (1) Initial register: 0x81:0xc3 + To add ptp table(bus0, devfn08) and program: 0x1c:0xf0, 0x20:0xf0, 0x21:0xff, 0x24:0xf0, 0x25:0xff, 0x34:0x80 + (2) After SPD, set registers: + (1) Second to write: 0x0d:0x08, 0xac:0x6e */ @@ -71,7 +76,7 @@ register_table: .byte 0x50, 0xfe .byte 0x51, 0xdf - .byte 0x52, 0xc8 + .byte 0x52, 0xc8 .byte 0x53, 0x98 .byte 0xf8, 0x22 .byte 0xf9, 0x42 @@ -114,8 +119,20 @@ register_table: .byte 0x75, 0x80 .byte 0x76, 0x80 .byte 0x79, 0xf0 + + .byte 0x81, 0xc3 .byte 0x0 /* end of table */ -ram_set_registers: + +ptp_table: + .byte 0x1c, 0xf0 + .byte 0x20, 0xf0 + .byte 0x21, 0xff + .byte 0x24, 0xf0 + .byte 0x25, 0xff + .byte 0x34, 0x80 + .byte 0x0 + +ram_set_registers: /* standard x86 loop on table until done code */ /* assumes that: devfn is 0 (safe on anything we've seen) */ /* which means addresses are a byte */ @@ -126,13 +143,27 @@ ram_set_registers: xor %eax, %eax movb (%esi), %al testb %al, %al - jz done_ram_set_registers +// jz done_ram_set_registers + jz ptp inc %esi movb (%esi), %dl PCI_WRITE_CONFIG_BYTE inc %esi jmp 1b +ptp: movl $ptp_table, %esi +2: + /* zero out eax. This is a must right here. */ + xor %eax, %eax + movb (%esi), %al + testb %al, %al + jz done_ram_set_registers + inc %esi + orl $0x0800, %eax + movb (%esi), %dl + PCI_WRITE_CONFIG_BYTE + inc %esi + jmp 2b // I forget why we need this, but we do mov $0xa55a5aa5, %eax @@ -314,7 +345,9 @@ spd_set_nbxcfg_done: orb $0x04, %dl ; \ movl $0x79, %eax ; \ PCI_WRITE_CONFIG_BYTE ; \ - CS_WRITE($0x7a, $0x01) + CS_WRITE($0x7a, $0x01) ; \ + CS_WRITE($0x0d, $0x08) ; \ + CS_WRITE($0xac, $0x6e) // CS_WRITE($0x6d, $0x21) ; \ // CS_WRITE($0x84, $0xc0)