diff --git a/mainboard/kontron/986lcd-m/stage1.c b/mainboard/kontron/986lcd-m/stage1.c index d0d7edadfa..649f6f23fc 100644 --- a/mainboard/kontron/986lcd-m/stage1.c +++ b/mainboard/kontron/986lcd-m/stage1.c @@ -203,90 +203,6 @@ static void early_superio_config_w83627thg(void) rawpnp_exit_ext_func_mode(port); } -static void rcba_config(void) -{ - /* Set up virtual channel 0 */ - //RCBA32(0x0014) = 0x80000001; - //RCBA32(0x001c) = 0x03128010; - - /* Device 1f interrupt pin register */ - RCBA32(0x3100) = 0x00042210; - /* Device 1d interrupt pin register */ - RCBA32(0x310c) = 0x00214321; - - /* dev irq route register */ - RCBA16(0x3140) = 0x0132; - RCBA16(0x3142) = 0x3241; - RCBA16(0x3144) = 0x0237; - RCBA16(0x3146) = 0x3210; - RCBA16(0x3148) = 0x3210; - - /* Enable IOAPIC */ - RCBA8(0x31ff) = 0x03; - - /* Enable upper 128bytes of CMOS */ - RCBA32(0x3400) = (1 << 2); - - /* Disable unused devices */ - RCBA32(0x3418) = 0x000e0063; - - /* Enable PCIe Root Port Clock Gate */ - // RCBA32(0x341c) = 0x00000001; -} - -static void early_ich7_init(void) -{ - u8 reg8; - u32 reg32; - - // program secondary mlt XXX byte? - pci_conf1_write_config8(PCI_BDF(0, 0x1e, 0), 0x1b, 0x20); - - // reset rtc power status - reg8 = pci_conf1_read_config8(PCI_BDF(0, 0x1f, 0), 0xa4); - reg8 &= ~(1 << 2); - pci_conf1_write_config8(PCI_BDF(0, 0x1f, 0), 0xa4, reg8); - - // usb transient disconnect - reg8 = pci_conf1_read_config8(PCI_BDF(0, 0x1f, 0), 0xad); - reg8 |= (3 << 0); - pci_conf1_write_config8(PCI_BDF(0, 0x1f, 0), 0xad, reg8); - - reg32 = pci_conf1_read_config32(PCI_BDF(0, 0x1d, 7), 0xfc); - reg32 |= (1 << 29) | (1 << 17); - pci_conf1_write_config32(PCI_BDF(0, 0x1d, 7), 0xfc, reg32); - - reg32 = pci_conf1_read_config32(PCI_BDF(0, 0x1d, 7), 0xdc); - reg32 |= (1 << 31) | (1 << 27); - pci_conf1_write_config32(PCI_BDF(0, 0x1d, 7), 0xdc, reg32); - - RCBA32(0x0088) = 0x0011d000; - RCBA16(0x01fc) = 0x060f; - RCBA32(0x01f4) = 0x86000040; - RCBA32(0x0214) = 0x10030549; - RCBA32(0x0218) = 0x00020504; - RCBA8(0x0220) = 0xc5; - reg32 = RCBA32(0x3410); - reg32 |= (1 << 6); - RCBA32(0x3410) = reg32; - reg32 = RCBA32(0x3430); - reg32 &= ~(3 << 0); - reg32 |= (1 << 0); - RCBA32(0x3430) = reg32; - RCBA32(0x3418) |= (1 << 0); - RCBA16(0x0200) = 0x2008; - RCBA8(0x2027) = 0x0d; - RCBA16(0x3e08) |= (1 << 7); - RCBA16(0x3e48) |= (1 << 7); - RCBA32(0x3e0e) |= (1 << 7); - RCBA32(0x3e4e) |= (1 << 7); - - // next step only on ich7m b0 and later: - reg32 = RCBA32(0x2034); - reg32 &= ~(0x0f << 16); - reg32 |= (5 << 16); - RCBA32(0x2034) = reg32; -} void hardware_stage1(void) { void early_superio_config_w83627thg(void); diff --git a/northbridge/intel/i945/raminit.c b/northbridge/intel/i945/raminit.c index bab289bfc5..84325db77a 100644 --- a/northbridge/intel/i945/raminit.c +++ b/northbridge/intel/i945/raminit.c @@ -26,8 +26,6 @@ #include #include #include -#include -#include #include #include #include diff --git a/northbridge/intel/i945/stage1.c b/northbridge/intel/i945/stage1.c index d8b864ee7e..8fc390ed3f 100644 --- a/northbridge/intel/i945/stage1.c +++ b/northbridge/intel/i945/stage1.c @@ -550,7 +550,7 @@ static void ich7_setup_pci_express(void) pci_conf1_write_config32(PCI_BDF(0, 0x1c, 0), 0xd8, 0x00110000); } -static void i945_early_initialization(void) +void i945_early_initialization(void) { /* Print some chipset specific information */ i945_detect_chipset(); @@ -562,7 +562,7 @@ static void i945_early_initialization(void) RCBA32(GCS) &= (~0x04); } -static void i945_late_initialization(void) +void i945_late_initialization(void) { i945_setup_egress_port(); diff --git a/southbridge/intel/i82801gx/stage1_smbus.c b/southbridge/intel/i82801gx/stage1_smbus.c index 04a5d6bb8b..8ae29eec0b 100644 --- a/southbridge/intel/i82801gx/stage1_smbus.c +++ b/southbridge/intel/i82801gx/stage1_smbus.c @@ -30,7 +30,7 @@ #include #include "i82801gx.h" -static void enable_smbus(void) +void enable_smbus(void) { u32 dev;