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riscv: enable counters via m[us]counteren

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The user and supervisor counters could not be safely enabled
before as the register numbers were not finalized. Now that
everyone agrees, we can enable them. Until we are sure the
toolchains are caught up, we use the hardcode name with
the register names in comments. As soon as toolchains
settle down we'll do one more pass and convert to
the symbolic names.

Tested on lowrisc bitstream and SPIKE simulator.

Change-Id: I21fe5cac44fafe4b7806e004c179aa27541be4b6
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-on: https://review.coreboot.org/17920
Tested-by: build bot (Jenkins)
Reviewed-by: Alex Bradbury <asb@lowrisc.org>
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-by: Andrew Waterman <aswaterman@gmail.com>
This commit is contained in:
Ronald G. Minnich 2016-12-19 09:06:00 -08:00
parent 41f6690239
commit f171e6645d
1 changed files with 8 additions and 10 deletions
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18
src/arch/riscv/virtual_memory.c
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@ -310,14 +310,12 @@ void mstatus_init(void)
set_csr(medeleg, delegate);
/* Enable all user/supervisor-mode counters */
/* We'll turn these on once lowrisc gets their bitstream up to
* 1.9. Right now there's no agreement on the values for these
* architectural registers.
*/
// write_csr(mscounteren, 0b111);
// write_csr(mucounteren, 0b111);
// for SPIKE:
// write_csr(/*mscounteren*/0x321, 0b111);
// Enable all user/supervisor-mode counters using
// v1.9.1 register addresses.
// They moved from the earlier spec.
// Until we trust our toolchain use the hardcoded constants.
// These were in flux and people who get the older toolchain
// will have difficult-to-debug failures.
write_csr(/*mucounteren*/0x320, 7);
write_csr(/*mscounteren*/0x321, 7);
}