From f0ee264dc2a237d006a350471c4ac2ac1ec6c265 Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Sun, 16 Oct 2016 10:58:01 +0200 Subject: [PATCH] UPSTREAM: nb/i945/raminit: Add fix for clock crossing for 800MHz FSB CPU The cross clocking of 800MHz FSB CPU with 667MHz RAM was incorrect. The result is that 800MHz FSB CPUs now properly work with 667MHz RAM. Value taken from vendor bios on ga-945gcm-s2l and suggested by Haouas Elyes. BUG=None BRANCH=None TEST=None Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/17038 Tested-by: build bot (Jenkins) Reviewed-by: HAOUAS Elyes Reviewed-by: Paul Menzel Reviewed-by: Nico Huber Change-Id: I56c12af50c75a735af0150a4e7bce4faacc93648 Reviewed-on: https://chromium-review.googlesource.com/400799 Commit-Ready: Furquan Shaikh Tested-by: Furquan Shaikh Reviewed-by: Aaron Durbin --- src/northbridge/intel/i945/raminit.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/northbridge/intel/i945/raminit.c b/src/northbridge/intel/i945/raminit.c index 1ec2dc5ef4..dbd5d42089 100644 --- a/src/northbridge/intel/i945/raminit.c +++ b/src/northbridge/intel/i945/raminit.c @@ -2261,7 +2261,7 @@ static void sdram_program_clock_crossing(void) 0x02010804, 0x00000000, /* DDR400 FSB800 */ 0x00010402, 0x00000000, /* DDR533 FSB800 */ - 0x04020180, 0x00000008, /* DDR667 FSB800 */ + 0x04020130, 0x00000008, /* DDR667 FSB800 */ 0x00020904, 0x00000000, /* DDR400 FSB1066 */ 0x02010804, 0x00000000, /* DDR533 FSB1066 */