mirror of
https://github.com/fail0verflow/switch-coreboot.git
synced 2025-05-04 01:39:18 -04:00
IRQ stuff.
This commit is contained in:
Greg Watson
parent
08d9a1daf3
commit
f0c291eef7
4 changed files with 183 additions and 13 deletions
54
src/arch/ppc/include/arch/pirq_routing.h
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54
src/arch/ppc/include/arch/pirq_routing.h
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@ -0,0 +1,54 @@
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#ifndef ARCH_PIRQ_ROUTING_H
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#define ARCH_PIRQ_ROUTING_H
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#include <types.h>
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#define PIRQ_SIGNATURE (('$' << 0) + ('P' << 8) + ('I' << 16) + ('R' << 24))
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#define PIRQ_VERSION 0x0100
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struct irq_info {
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u8 bus, devfn; /* Bus, device and function */
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struct {
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u8 link; /* IRQ line ID, chipset dependent, 0=not routed */
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u16 bitmap; /* Available IRQs */
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} __attribute__((packed)) irq[4];
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u8 slot; /* Slot number, 0=onboard */
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u8 rfu;
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} __attribute__((packed));
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#if defined(IRQ_SLOT_COUNT)
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#define IRQ_SLOTS_COUNT IRQ_SLOT_COUNT
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#elif (__GNUC__ < 3)
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#define IRQ_SLOTS_COUNT 1
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#else
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#define IRQ_SLOTS_COUNT
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#endif
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struct irq_routing_table {
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u32 signature; /* PIRQ_SIGNATURE should be here */
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u16 version; /* PIRQ_VERSION */
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u16 size; /* Table size in bytes */
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u8 rtr_bus, rtr_devfn; /* Where the interrupt router lies */
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u16 exclusive_irqs; /* IRQs devoted exclusively to PCI usage */
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u16 rtr_vendor, rtr_device; /* Vendor and device ID of interrupt router */
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u32 miniport_data; /* Crap */
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u8 rfu[11];
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u8 checksum; /* Modulo 256 checksum must give zero */
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struct irq_info slots[IRQ_SLOTS_COUNT];
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} __attribute__((packed));
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extern const struct irq_routing_table intel_irq_routing_table;
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#if defined(DEBUG) && defined(HAVE_PIRQ_TABLE)
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void check_pirq_routing_table(void);
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#else
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#define check_pirq_routing_table() do {} while(0)
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#endif
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#if defined(HAVE_PIRQ_TABLE)
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unsigned long copy_pirq_routing_table(unsigned long start);
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#else
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#define copy_pirq_routing_table(start) (start)
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#endif
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#endif /* ARCH_PIRQ_ROUTING_H */
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94
src/arch/ppc/lib/pirq_routing.c
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94
src/arch/ppc/lib/pirq_routing.c
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@ -0,0 +1,94 @@
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#include <printk.h>
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#include <pci.h>
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#include <arch/pirq_routing.h>
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#include <string.h>
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#ifdef DEBUG
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void check_pirq_routing_table(void)
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{
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const u8 *addr;
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const struct irq_routing_table *rt;
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int i;
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u8 sum;
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printk_info("Checking IRQ routing tables...\n");
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#ifdef(IRQ_SLOT_COUNT)
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if (sizeof(intel_irq_routing_table) != intel_irq_routing_table.size) {
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printk_warning("Inconsistent IRQ routing table size\n");
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}
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#endif
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rt = &intel_irq_routing_table;
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addr = (u8 *)rt;
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sum = 0;
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for (i = 0; i < rt->size; i++)
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sum += addr[i];
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printk_debug("%s:%6d:%s() - irq_routing_table located at: 0x%p\n",
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__FILE__, __LINE__, __FUNCTION__, addr);
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sum = (unsigned char)(rt->checksum-sum);
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if (sum != rt->checksum) {
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printk_warning("%s:%6d:%s() - "
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"checksum is: 0x%02x but should be: 0x%02x\n",
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__FILE__, __LINE__, __FUNCTION__, rt->checksum, sum);
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}
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if (rt->signature != PIRQ_SIGNATURE || rt->version != PIRQ_VERSION ||
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rt->size % 16 || rt->size < sizeof(struct irq_routing_table)) {
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printk_warning("%s:%6d:%s() - "
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"Interrupt Routing Table not valid\n",
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__FILE__, __LINE__, __FUNCTION__);
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return;
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}
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sum = 0;
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for (i=0; i<rt->size; i++)
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sum += addr[i];
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if (sum) {
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printk_warning("%s:%6d:%s() - "
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"checksum error in irq routing table\n",
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__FILE__, __LINE__, __FUNCTION__);
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}
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printk_info("done.\n");
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}
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int verify_copy_pirq_routing_table(unsigned long addr)
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{
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int i;
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u8 *rt_orig, *rt_curr;
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rt_curr = (u8*)addr;
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rt_orig = (u8*)&intel_irq_routing_table;
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printk_info("Verifing priq routing tables copy at 0x%x...", addr);
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for (i = 0; i < intel_irq_routing_table.size; i++) {
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if (*(rt_curr + i) != *(rt_orig + i)) {
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printk_info("failed\n");
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return -1;
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}
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}
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printk_info("succeed\n");
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return 0;
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}
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#else
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#define verify_copy_pirq_routing_table(addr)
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#endif
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unsigned long copy_pirq_routing_table(unsigned long addr)
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{
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/* Align the table to be 16 byte aligned. */
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addr += 15;
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addr &= ~15;
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/* This table must be betweeen 0xf0000 & 0x100000 */
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printk_info("Copying IRQ routing tables to 0x%x...", addr);
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memcpy((void *)addr, &intel_irq_routing_table, intel_irq_routing_table.size);
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printk_info("done.\n");
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verify_copy_pirq_routing_table(addr);
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return addr + intel_irq_routing_table.size;
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}
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26
src/mainboard/motorola/sandpoint/irq_tables.c
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26
src/mainboard/motorola/sandpoint/irq_tables.c
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@ -0,0 +1,26 @@
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#include <arch/pirq_routing.h>
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const struct irq_routing_table ppc_irq_routing_table = {
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PIRQ_SIGNATURE, /* u32 signature */
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PIRQ_VERSION, /* u16 version */
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32+16*9, /* u16 Table size 32+(16*devices) */
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0x00, /* u8 Bus 0 */
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0xf8, /* u8 Device 1, Function 0 */
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0x0000, /* u16 reserve IRQ for PCI */
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0x1057, /* u16 Vendor - Motorola */
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0x0004, /* Device ID - MPC107 */
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0x00000000, /* u32 miniport_data */
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{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */
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IRQ_CHECKSUM, /* u8 checksum - mod 256 checksum must give zero */
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{ /* bus, devfn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */
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{0x00, 0x10, {{0x62, 0xdeb8}, {0x62, 0xdeb8}, {0x62, 0xdeb8}, {0x62, 0xdeb8}}, 0x00, 0x00},
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{0x04, 0x40, {{0x68, 0xdeb8}, {0x69, 0xdeb8}, {0x6a, 0xdeb8}, {0x6b, 0xdeb8}}, 0x01, 0x00},
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{0x04, 0x38, {{0x60, 0xdeb8}, {0x61, 0xdeb8}, {0x62, 0xdeb8}, {0x63, 0xdeb8}}, 0x02, 0x00},
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{0x04, 0x08, {{0x61, 0xdeb8}, {0x62, 0xdeb8}, {0x63, 0xdeb8}, {0x60, 0xdeb8}}, 0x03, 0x00},
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{0x04, 0x10, {{0x62, 0xdeb8}, {0x63, 0xdeb8}, {0x60, 0xdeb8}, {0x61, 0xdeb8}}, 0x04, 0x00},
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{0x04, 0x18, {{0x63, 0xdeb8}, {0x60, 0xdeb8}, {0x61, 0xdeb8}, {0x62, 0xdeb8}}, 0x05, 0x00},
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{0x04, 0x20, {{0x60, 0xdeb8}, {0x61, 0xdeb8}, {0x62, 0xdeb8}, {0x63, 0xdeb8}}, 0x06, 0x00},
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{0x03, 0x20, {{0x60, 0xdeb8}, {0x61, 0xdeb8}, {0x62, 0xdeb8}, {0x63, 0xdeb8}}, 0x07, 0x00},
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{0x00, 0xf8, {{0x60, 0xdeb8}, {0x61, 0xdeb8}, {0x6b, 0xdeb8}, {0x63, 0xdeb8}}, 0x08, 0x00}
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}
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};
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@ -56,10 +56,7 @@ extern struct pci_ops pci_direct_ppc;
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void southbridge_early_init(void)
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{
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struct pci_dev *devbusfn;
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unsigned char reg8;
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unsigned short reg16;
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unsigned int reg32;
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/*
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* Set ISA memory space
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@ -68,7 +65,7 @@ void southbridge_early_init(void)
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/* 16 MB ISA memory space */
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reg8 |= (IPADCR_IPATOM4 | IPADCR_IPATOM5 | IPADCR_IPATOM6 | IPADCR_IPATOM7);
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reg8 &= ~IPADCR_MBE512;
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pci_direct_ppc.read_byte(0, 0x58, WINBOND_IPADCR, reg8);
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pci_direct_ppc.write_byte(0, 0x58, WINBOND_IPADCR, ®8);
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}
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void southbridge_init(void)
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@ -113,14 +110,14 @@ void southbridge_init(void)
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/*
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* Interrupt routing:
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* - IDE -> INTC/INTD
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* - INTA -> IRQ 5
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* - INTB -> IRQ 6
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* - INTC -> IRQ 7
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* - INTD -> IRQ 8
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* - IDE -> 9/0
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* - INTA -> IRQ 10
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* - INTB -> IRQ 11
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* - INTC -> IRQ 14
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* - INTD -> IRQ 15
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*/
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pci_write_config_byte(devbusfn, WINBOND_IDEIRCR, 0x0);
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pci_write_config_word(devbusfn, WINBOND_PCIIRCR, 0x5678);
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pci_write_config_byte(devbusfn, WINBOND_IDEIRCR, 0x90);
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pci_write_config_word(devbusfn, WINBOND_PCIIRCR, 0xABEF);
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/*
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* Read IDE bus offsets from function 1 device.
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@ -144,8 +141,7 @@ void southbridge_init(void)
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* Secondary port Mode 0 ~P1F16
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*/
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pci_read_config_dword(devbusfn, WINDOND_IDECSR, ®32);
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reg32 |= IDECSR_LEGIRQ;
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reg32 &= ~(IDECSR_P1EN | IDECSR_P1F16);
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reg32 &= ~(IDECSR_LEGIRQ | IDECSR_P1EN | IDECSR_P1F16);
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pci_write_config_dword(devbusfn, WINDOND_IDECSR, reg32);
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pci_read_config_dword(devbusfn, PCI_BASE_ADDRESS_0, &ide_bus_offset[0]);
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