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- Fixes for the code that reduces the number of banks processed by the code.

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This commit is contained in:
Eric W. Biederman 2002-10-26 02:23:20 +00:00
parent 8386fee707
commit f0bc1ed2a5
1 changed files with 10 additions and 19 deletions
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27
src/northbridge/intel/E7500/raminit.inc
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@ -525,12 +525,7 @@ ram_set_rcomp_regs:
/* not sure this next section is correct, documentation on device 0
function 3, register 80 is lacking. */
movl %eax, %ecx
#if 0
CONSOLE_DEBUG_TX_HEX32(%ecx)
movl $0x0380, %eax /* read function 3 offset 80 */
PCI_READ_CONFIG_DWORD
movl %eax, %ecx
#endif
andl $0xff01ffff, %ecx
shrl $7, %eax
andl $0x00fe0000, %eax
@ -547,12 +542,7 @@ ram_set_rcomp_regs:
orl $0x80008000, %ecx
movl $0x0380, %eax
PCI_WRITE_CONFIG_DWORD /* enable mode overide */
#if 0
movl $0x0380, %eax /* read function 3 offset 80 */
PCI_READ_CONFIG_DWORD
movl %eax, %ecx
CONSOLE_DEBUG_TX_HEX32(%ecx)
#endif
movl $0x0088, %eax /* enable periodic compensaion */
PCI_READ_CONFIG_BYTE
orb $(1<<7), %al
@ -1647,17 +1637,18 @@ spd_get_dimm_size:
jbe spd_get_dimm_size
/* now, fill in DRBs where no physical slot exists */
movl $(SMBUS_MEM_DEVICE_END - SMBUS_MEM_DEVICE_START), %ecx
addl %ecx, %ecx
addl $0x61, %ecx
1:
incl %eax
cmpb $LAST_DRB_SLOT, %al
jg spd_set_ram_size_computed
incl %ecx
cmpl $LAST_DRB_SLOT, %ecx
ja spd_set_ram_size_computed
movl %ebp, %edx
movl %eax, %ecx
PCI_WRITE_CONFIG_BYTE
movl %ecx, %eax
PCI_WRITE_CONFIG_BYTE
jmp 1b
spd_set_ram_size_computed:
/* For now hardset everything at 128MB boundaries */
/* %ebp has the ram size in multiples of 64MB */