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UPSTREAM: intel sandy/ivy: Change CRC used to detect DIMM replacement
Switch to use CRC of unique identifier section SPD[117..127], remaining area of SPD data is ignored. BUG=None BRANCH=None TEST=None Signed-off-by: Kysti Mlkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/17487 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Change-Id: If4b43183f99f5f911ae6c311b43c29a72b9922e2 Reviewed-on: https://chromium-review.googlesource.com/413255 Commit-Ready: Furquan Shaikh <furquan@chromium.org> Tested-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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1 changed files with 2 additions and 2 deletions
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@ -355,7 +355,7 @@ static int verify_crc16_spds_ddr3(spd_raw_data *spd, ramctr_timing *ctrl)
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for (slot = 0; slot < NUM_SLOTS; slot++) {
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spd_slot = 2 * channel + slot;
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match &= ctrl->spd_crc[channel][slot] ==
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spd_ddr3_calc_crc(spd[spd_slot], sizeof(spd_raw_data));
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spd_ddr3_calc_unique_crc(spd[spd_slot], sizeof(spd_raw_data));
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}
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}
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return match;
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@ -415,7 +415,7 @@ static void dram_find_spds_ddr3(spd_raw_data *spd, ramctr_timing *ctrl)
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/* fill in CRC16 for MRC cache */
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ctrl->spd_crc[channel][slot] =
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spd_ddr3_calc_crc(spd[spd_slot], sizeof(spd_raw_data));
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spd_ddr3_calc_unique_crc(spd[spd_slot], sizeof(spd_raw_data));
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if (dimm->dimm[channel][slot].dram_type != SPD_MEMORY_TYPE_SDRAM_DDR3) {
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// set dimm invalid
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