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UPSTREAM: intel sandy/ivy: Change CRC used to detect DIMM replacement

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Switch to use CRC of unique identifier section SPD[117..127],
remaining area of SPD data is ignored.

BUG=None
BRANCH=None
TEST=None

Signed-off-by: Kysti Mlkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/17487
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>

Change-Id: If4b43183f99f5f911ae6c311b43c29a72b9922e2
Reviewed-on: https://chromium-review.googlesource.com/413255
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Kyösti Mälkki 2016-11-18 18:52:04 +02:00 • committed by chrome-bot
parent af0dc15b2a
commit eef4f98e5b
1 changed files with 2 additions and 2 deletions
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4
src/northbridge/intel/sandybridge/raminit.c
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@ -355,7 +355,7 @@ static int verify_crc16_spds_ddr3(spd_raw_data *spd, ramctr_timing *ctrl)
for (slot = 0; slot < NUM_SLOTS; slot++) {
spd_slot = 2 * channel + slot;
match &= ctrl->spd_crc[channel][slot] ==
spd_ddr3_calc_crc(spd[spd_slot], sizeof(spd_raw_data));
spd_ddr3_calc_unique_crc(spd[spd_slot], sizeof(spd_raw_data));
}
}
return match;
@ -415,7 +415,7 @@ static void dram_find_spds_ddr3(spd_raw_data *spd, ramctr_timing *ctrl)
/* fill in CRC16 for MRC cache */
ctrl->spd_crc[channel][slot] =
spd_ddr3_calc_crc(spd[spd_slot], sizeof(spd_raw_data));
spd_ddr3_calc_unique_crc(spd[spd_slot], sizeof(spd_raw_data));
if (dimm->dimm[channel][slot].dram_type != SPD_MEMORY_TYPE_SDRAM_DDR3) {
// set dimm invalid