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rockchip: rk3399: use apll define instead apll_l define

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use apll define instead apll_l define, so we can reuse it when
do apll_b setting.

BRANCH=None
BUG=None
TEST=Boot from Gru

Change-Id: I63966e98af48eaf49837eb0b781eea001a376ef4
Signed-off-by: Lin Huang <hl@rock-chips.com>
Reviewed-on: https://chromium-review.googlesource.com/356398
Reviewed-by: Douglas Anderson <dianders@chromium.org>
Tested-by: Douglas Anderson <dianders@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Commit-Queue: Douglas Anderson <dianders@chromium.org>
This commit is contained in:
Lin Huang 2016-06-28 14:19:18 +08:00 • committed by Douglas Anderson
parent 116ae863a5
commit eb578110d1
3 changed files with 13 additions and 13 deletions
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2
src/soc/rockchip/rk3399/bootblock.c
View file

@ -22,7 +22,7 @@
void bootblock_soc_init(void)
{
rkclk_init();
rkclk_configure_cpu(APLL_L_600_MHZ);
rkclk_configure_cpu(APLL_600_MHZ);
/* all ddr range non-secure */
write32(&rk3399_pmusgrf->ddr_rgn_con[16], 0xff << 16 | 0);

16
src/soc/rockchip/rk3399/clock.c
View file

@ -47,12 +47,12 @@ static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 2, 2, 1);
static const struct pll_div cpll_init_cfg = PLL_DIVISORS(CPLL_HZ, 1, 2, 2);
static const struct pll_div ppll_init_cfg = PLL_DIVISORS(PPLL_HZ, 2, 2, 1);
static const struct pll_div apll_l_1600_cfg = PLL_DIVISORS(1600*MHz, 3, 1, 1);
static const struct pll_div apll_l_600_cfg = PLL_DIVISORS(600*MHz, 1, 2, 1);
static const struct pll_div apll_1600_cfg = PLL_DIVISORS(1600*MHz, 3, 1, 1);
static const struct pll_div apll_600_cfg = PLL_DIVISORS(600*MHz, 1, 2, 1);
static const struct pll_div *apll_l_cfgs[] = {
[APLL_L_1600_MHZ] = &apll_l_1600_cfg,
[APLL_L_600_MHZ] = &apll_l_600_cfg,
static const struct pll_div *apll_cfgs[] = {
[APLL_1600_MHZ] = &apll_1600_cfg,
[APLL_600_MHZ] = &apll_600_cfg,
};
enum {
@ -487,16 +487,16 @@ void rkclk_init(void)
HCLK_PERILP1_PLL_SEL_SHIFT));
}
void rkclk_configure_cpu(enum apll_l_frequencies apll_l_freq)
void rkclk_configure_cpu(enum apll_frequencies apll_l_freq)
{
u32 aclkm_div;
u32 pclk_dbg_div;
u32 atclk_div;
u32 apll_l_hz;
apll_l_hz = apll_l_cfgs[apll_l_freq]->freq;
apll_l_hz = apll_cfgs[apll_l_freq]->freq;
rkclk_set_pll(&cru_ptr->apll_l_con[0], apll_l_cfgs[apll_l_freq]);
rkclk_set_pll(&cru_ptr->apll_l_con[0], apll_cfgs[apll_l_freq]);
aclkm_div = div_round_up(apll_l_hz, ACLKM_CORE_HZ) - 1;

8
src/soc/rockchip/rk3399/include/soc/clock.h
View file

@ -96,14 +96,14 @@ static struct rk3399_cru_reg * const cru_ptr = (void *)CRU_BASE;
#define PWM_CLOCK_HZ PMU_PCLK_HZ
enum apll_l_frequencies {
APLL_L_1600_MHZ,
APLL_L_600_MHZ,
enum apll_frequencies {
APLL_1600_MHZ,
APLL_600_MHZ,
};
void rkclk_init(void);
int rkclk_configure_vop_dclk(u32 vop_id, u32 dclk_hz);
void rkclk_configure_cpu(enum apll_l_frequencies apll_l_freq);
void rkclk_configure_cpu(enum apll_frequencies apll_l_freq);
void rkclk_configure_ddr(unsigned int hz);
void rkclk_configure_emmc(void);
void rkclk_configure_i2s(unsigned int hz);