diff --git a/romimages/RON_TYAN_S1834/Makefile b/romimages/RON_TYAN_S1834/Makefile new file mode 100644 index 0000000000..46f6955318 --- /dev/null +++ b/romimages/RON_TYAN_S1834/Makefile @@ -0,0 +1,164 @@ +CPUFLAGS=-DPM133 -Di386 -Di486 -Di686 -Di586 -D__KERNEL__ +# Well, we have old silicon +CPUFLAGS += -DPM133_REV_CD_CE +CPUFLAGS += -DINTEL_BRIDGE_CONFIG +CPUFLAGS += -DINTEL_PPRO_MTRR +CPUFLAGS += -DPM133_NVRAM -DPM133_KEYBOARD +CPUFLAGS += -DNEWPCI +CPUFLAGS += -DSERIAL_CONSOLE +CPUFLAGS += -DDISABLE_SOUTHBRIDGE_COM_PORTS +# If you enable FIXED_AND_VARIABLE it never makes it to the kernel! +# you have to only enable variable. +#CPUFLAGS += -DENABLE_FIXED_AND_VARIABLE_MTRRS +CPUFLAGS += -DRAMTEST +# This makes it fail sooner ... +#CPUFLAGS += -DINBUF_COPY +CPUFLAGS += -DCMD_LINE='"ro root=/dev/hda1 console=ttyS0,115200 single "' + +TOP=../.. +INCLUDES=-nostdinc -I $(TOP)/src/include +NOOPT_CFLAGS=$(INCLUDES) $(CPUFLAGS) -Wall +CFLAGS=$(NOOPT_CFLAGS) -O2 + +OBJECTS=crt0.o hardwaremain.o linuxbiosmain.o +OBJECTS += mainboard.o mtrr.o subr.o fill_inbuf.o params.o +OBJECTS += southbridge.o northbridge.o superio.o +#OBJECTS += pci.o +OBJECTS += printk.o vsprintf.o +OBJECTS += newpci.o linuxpci.o +OBJECTS += cpuid.o +#OBJECTS += intel_irq_tables.o +OBJECTS += serial_subr.o +OBJECTS += mpspec.o +OBJECTS += microcode.o +OBJECTS += keyboard.o +LINUX=$(TOP)/../linux-2.4.0-test6.via/ + +LINK = ld -T ../../src/mainboard/tyan/s1834/ldscript.ld -o $@ $(OBJECTS) +CC=cc $(CFLAGS) +CCASM=cc -I$(TOP)/chip/intel $(CFLAGS) + +all: romimage +floppy: all + mcopy -o romimage a: +# here's the problem: we shouldn't assume we come up with more than +# 64K of FLASH up. SO we need a working linuxbios at the tail, and it will +# enable all flash and then gunzip the linuxbios. As a result, +# we need the vmlinux.bin.gz padded out and then cat the linuxbios.rom +# at then end. We always copy it to /tmp so that a waiting root shell +# can put it on the floppy (see ROOTDOIT) +romimage: linuxbios.rom vmlinux.bin.gz.block + cat vmlinux.bin.gz.block linuxbios.rom > romimage + cp romimage /tmp + +linuxbios.rom: linuxbios.strip mkrom + ./mkrom -s 64 -f -o linuxbios.rom linuxbios.strip + +linuxbios.strip: linuxbios + objcopy -O binary -R .note -R .comment -S linuxbios linuxbios.strip + +linuxbios: $(OBJECTS) vmlinux.bin.gz + @rm -f biosobject + $(LINK) + nm -n linuxbios > linuxbios.map + +# crt0 actually includes .inc files. +# For self-documenting purposes, we put the FULL PATH of the +# .inc files (relative to $TOP/src) in crt0.S. +# So, for example, earlymtrr.inc is included as cpu/p6/earlymtrr.inc +# To make this work, add the extra -I $(TOP)/src here. +crt0.s: ../../src/mainboard/tyan/s1834/crt0.S + $(CCASM) -I $(TOP)/src -E $< > crt0.s + +crt0.o : crt0.s + $(CCASM) -c crt0.s + +mkrom: $(TOP)/mkrom/mkrom.c + cc -o mkrom $< + +linuxbiosmain.o: $(TOP)/src/lib/linuxbiosmain.c + cc $(CFLAGS) -c $< + +mainboard.o: $(TOP)/src/mainboard/via/vt5292/mainboard.c + cc $(CFLAGS) -c $< + +fill_inbuf.o: $(TOP)/src/lib/fill_inbuf.c + cc $(CFLAGS) -c $< + +params.o: $(TOP)/src/lib/params.c + cc $(CFLAGS) $(LINUXINCLUDE) -c $< + +hardwaremain.o: $(TOP)/src/lib/hardwaremain.c + cc $(CFLAGS) -c $< + +southbridge.o: $(TOP)/src/southbridge/via/vt82c686/southbridge.c + cc $(CFLAGS) -c $< + +northbridge.o: $(TOP)/src/northbridge/via/vt8601/northbridge.c + cc $(CFLAGS) -c $< + +superio.o: $(TOP)/src/superio/winbond/w83977ef/superio.c + cc $(CFLAGS) -c $< + +pci.o: $(TOP)/src/lib/pci.c + cc $(CFLAGS) -c $< + +# not on this machine, not yet. +#intel_irq_tables.o: ../../chip/intel/intel_irq_tables.c +# cc $(CFLAGS) -o $@ -c $< + +mtrr.o: $(TOP)/src/cpu/p6/mtrr.c + cc $(CFLAGS) -c $< + +subr.o: $(TOP)/src/lib/subr.c + cc $(CFLAGS) -c $< + +keyboard.o: $(TOP)/src/pc80/keyboard.c + cc $(CFLAGS) -c $< + +cpuid.o: $(TOP)/src/cpu/p5/cpuid.c + cc $(CFLAGS) -c $< + +mpspec.o: $(TOP)/src/cpu/p6/mpspec.c + $(CC) $(CFLAGS) -c $< + +microcode.o: $(TOP)/src/cpu/p6/microcode.c + $(CC) $(CFLAGS) -c $< + +serial_subr.o: $(TOP)/src/lib/serial_subr.c + cc $(CFLAGS) -c $< + +printk.o: $(TOP)/src/lib/printk.c + cc $(CFLAGS) -c $< + +vsprintf.o: $(TOP)/src/lib/vsprintf.c + cc $(CFLAGS) -c $< + +newpci.o: $(TOP)/src/lib/newpci.c + cc $(CFLAGS) -c $< + +linuxpci.o: $(TOP)/src/lib/linuxpci.c + cc $(CFLAGS) -c $< + +vmlinux.bin.gz.block: vmlinux.bin.gz + dd conv=sync bs=448k if=vmlinux.bin.gz of=vmlinux.bin.gz.block +vmlinux.bin.gz: vmlinux.bin + gzip -f -3 vmlinux.bin + +vmlinux.bin: $(LINUX)/vmlinux + objcopy -O binary -R .note -R .comment -S $< vmlinux.bin + +alltags: + gctags ../inflate/*.c ../../lib/*.c ../../chip/intel/*.c + etags ../inflate/*.c ../../lib/*.c ../../chip/intel/*.c + + +clean:: + rm -f linuxbios.* vmlinux.* *.o mkrom xa? *~ linuxbios romimage crt0.s + rm -f a.out *.s *.l + rm -f TAGS tags + + + + + diff --git a/src/mainboard/tyan/s1834/crt0.S b/src/mainboard/tyan/s1834/crt0.S new file mode 100644 index 0000000000..46af6fbb62 --- /dev/null +++ b/src/mainboard/tyan/s1834/crt0.S @@ -0,0 +1,107 @@ +/* + * $ $ + * + */ + +#include +#include + +#include + +/* + * This is the entry code (the mkrom(8) utility makes a jumpvector + * to this adddess. + * + * When we get here we are in x86 real mode. + * + * %cs = 0xf000 %ip = 0x0000 + * %ds = 0x0000 %es = 0x0000 + * %dx = 0x0yxx (y = 3 for i386, 5 for pentium, 6 for P6, + * where x is undefined) + * %fl = 0x0002 + */ + .text + .code16 + +#include + +#include + +#include + + TTYS0_TX_STRING($ttyS0_test) + + /* initialize the RAM */ + /* different for each motherboard */ + +#include + +#ifdef RAMTEST +#include + +#include + mov $0x00000000, %eax + mov $0x0009ffff, %ebx + mov $16, %ecx + + CALLSP(ramtest) +#endif +/* + * Copy data into RAM and clear the BSS. Since these segments + * isn't really that big we just copy/clear using bytes, not + * double words. + */ + intel_chip_post_macro(0x11) /* post 11 */ + TTYS0_TX_STRING($str_after_ram) + + cld /* clear direction flag */ + leal EXT(_ldata), %esi + leal EXT(_data), %edi + movl $EXT(_eldata), %ecx + subl %esi, %ecx + jz .Lnodata /* should not happen */ + rep + movsb +.Lnodata: + intel_chip_post_macro(0x12) /* post 12 */ + TTYS0_TX_STRING($str_after_copy) + + /** clear stack */ + xorl %edi, %edi + movl $_PDATABASE, %ecx + xorl %eax, %eax + rep + stosb + /** clear bss */ + leal EXT(_bss), %edi + movl $EXT(_ebss), %ecx + subl %edi, %ecx + jz .Lnobss + xorl %eax, %eax + rep + stosb +.Lnobss: + +/* + * Now we are finished. Memory is up, data is copied and + * bss is cleared. Now we call the ``main´´ routine and + * let it do the rest. + */ + intel_chip_post_macro(0xfe) /* post fe */ + TTYS0_TX_STRING($str_pre_main) + + /* set new stack */ + movl $_PDATABASE, %esp +/* memory is up. Let's do the rest in C -- much easier. */ + call EXT(intel_main) + /*NOTREACHED*/ +.Lhlt: hlt + jmp .Lhlt + +ttyS0_test: .string "\r\n\r\nHello world!!\r\n" +str_after_ram: .string "Ram Initialize?\r\n" +str_after_copy: .string "after copy?\r\n" +str_pre_main: .string "before main\r\n" +newline: .string "\r\n" + + diff --git a/src/mainboard/tyan/s1834/ldscript.ld b/src/mainboard/tyan/s1834/ldscript.ld new file mode 100644 index 0000000000..c1669e1d79 --- /dev/null +++ b/src/mainboard/tyan/s1834/ldscript.ld @@ -0,0 +1,116 @@ +/* + * Bootstrap code for the STPC Consumer + * Copyright (c) 1999 by Net Insight AB. All Rights Reserved. + * + * $Id$ + * + */ +/* oh, barf. This won't work if all you use is .o's. -- RGM */ + +/* + * Written by Johan Rydberg, based on work by Daniel Kahlin. + */ +/* + * We use ELF as output format. So that we can + * debug the code in some form. + */ +OUTPUT_FORMAT("elf32-i386", "elf32-i386", "elf32-i386") +OUTPUT_ARCH(i386) + +/* + * Memory map: + * + * 0x00000 (4*4096 bytes) : stack + * 0x04000 (4096 bytes) : private data + * 0x05000 : data space + * 0x90000 : kernel stack + * 0xf0000 (64 Kbyte) : EPROM + */ +MEMORY +{ + ram (rwx) : ORIGIN = 0x00000000, LENGTH = 128M /* 128 MB memory is + * max for STPC */ + rom (rx) : ORIGIN = 0x000f0000, LENGTH = 128K /* 128 K EPROM */ +} + +_PDATABASE = 0x04000; +_RAMBASE = 0x05000; +_KERNSTK = 0x90000; +/* should be parameterized but is not, yuck! */ +/* +_ROMBASE = 0xe0000; + */ +_ROMBASE = 0xf0000; + +/* + * Entry point is not really nececary, since the mkrom(8) + * tool creates a entry point that jumps to $0xc000:0x0000. + */ +/* baloney, but ... RGM*/ +ENTRY(_start) + +SECTIONS { + /* + * First we place the code and read only data (typically const declared). + * This get placed in rom. + */ + .text _ROMBASE : { + _text = .; + *(.text); + *(.rodata); + _etext = .; + } + + _pdata = .; + +/* + .pdata _PDATABASE : AT ( LOADADDR(.text) + SIZEOF(.text) + + SIZEOF(.rodata)) { + */ + .pdata _PDATABASE : AT ( _etext ) { + *(.pdata); + } + + _epdata = LOADADDR(.pdata) + SIZEOF(.pdata); + + /* + * After the code we place initialized data (typically initialized + * global variables). This gets copied into ram by startup code. + * __data_start and __data_end shows where in ram this should be placed, + * whereas __data_loadstart and __data_loadend shows where in rom to + * copy from. + */ + .data _RAMBASE : AT ( LOADADDR(.pdata) + SIZEOF(.pdata) ) { + _data = .; + *(.data) + *(.sdata) + *(.sdata2) + *(.got) + _edata = .; + } + + _ldata = LOADADDR(.data); + _eldata = LOADADDR(.data) + SIZEOF(.data); + + /* + * bss does not contain data, it is just a space that should be zero + * initialized on startup. (typically uninitialized global variables) + * crt0.S fills between __bss_start and __bss_end with zeroes. + */ + .bss ( ADDR(.data) + SIZEOF(.data) ) : { + _bss = .; + *(.bss) + *(.sbss) + *(COMMON) + _ebss = .; + _heap = .; + } +} + +/* + * This provides the start and end address for the whole image + */ +_image = LOADADDR(.text); +_eimage = LOADADDR(.data) + SIZEOF(.data); + +/* EOF */ diff --git a/src/mainboard/tyan/s1834/mainboard.c b/src/mainboard/tyan/s1834/mainboard.c new file mode 100644 index 0000000000..dc2118cfc9 --- /dev/null +++ b/src/mainboard/tyan/s1834/mainboard.c @@ -0,0 +1,6 @@ +void +mainboard_fixup() +{ + void southbridge_fixup(void); + southbridge_fixup(); +} diff --git a/src/southbridge/via/vt82c686/southbridge.c b/src/southbridge/via/vt82c686/southbridge.c index 1ffc29f7f3..dc35153f6d 100644 --- a/src/southbridge/via/vt82c686/southbridge.c +++ b/src/southbridge/via/vt82c686/southbridge.c @@ -50,6 +50,7 @@ void southbridge_fixup() enables |= 0x80; pcibios_write_config_byte(0, devfn, 0x81, enables); +#ifndef DISABLE_SOUTHBRIDGE_COM_PORTS // enable com1 and com2. enables = pcibios_read_config_byte(0, devfn, 0x83, &enables); // 0x80 is enable com port b, 0x1 is to make it com2, 0x8 is enable com port a as com1 @@ -59,6 +60,7 @@ void southbridge_fixup() // set com1 to 115 kbaud // not clear how to do this yet. // forget it; done in assembly. +#endif // enable IDE, since Linux won't do it. // First do some more things to devfn (7,0) // note: this should already be cleared, according to the book.