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git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1570 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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1 changed files with 58 additions and 57 deletions
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@ -17,51 +17,52 @@
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#include "lib/delay.c"
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#include "lib/delay.c"
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#include "cpu/p6/boot_cpu.c"
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#include "cpu/p6/boot_cpu.c"
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#include "northbridge/amd/amdk8/reset_test.c"
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#include "northbridge/amd/amdk8/reset_test.c"
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#include "northbridge/amd/amdk8/debug.c"
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#include "northbridge/amd/amdk8/debug.c"
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#include "northbridge/amd/amdk8/cpu_rev.c"
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#include "northbridge/amd/amdk8/cpu_rev.c"
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#include "superio/winbond/w83627hf/w83627hf_early_serial.c"
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#include "superio/winbond/w83627hf/w83627hf_early_serial.c"
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#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
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#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
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static void hard_reset(void)
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static void hard_reset(void)
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{
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{
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set_bios_reset();
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set_bios_reset();
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/* enable cf9 */
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/* enable cf9 */
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pci_write_config8(PCI_DEV(0, 0x02, 3), 0x41, 0xf1);
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pci_write_config8(PCI_DEV(0, 0x02, 3), 0x41, 0xf1);
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/* reset */
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/* reset */
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outb(0x0e, 0x0cf9);
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outb(0x0e, 0x0cf9);
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}
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}
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static void soft_reset(void)
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static void soft_reset(void)
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{
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{
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set_bios_reset();
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set_bios_reset();
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pci_write_config8(PCI_DEV(0, 0x02, 0), 0x47, 1);
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pci_write_config8(PCI_DEV(0, 0x02, 0), 0x47, 1);
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}
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}
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#define REV_B_RESET 0
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#define REV_B_RESET 0
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static void memreset_setup(void)
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static void memreset_setup(void)
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{
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{
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if (is_cpu_pre_c0()) {
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if (is_cpu_pre_c0()) {
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outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 16); //REVC_MEMRST_EN=0
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outb((0 << 7) | (0 << 6) | (0 << 5) | (0 << 4) | (1 << 2) | (0 << 0), SMBUS_IO_BASE + 0xc0 + 16); //REVC_MEMRST_EN=0
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}
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} else {
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else {
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outb((0 << 7) | (0 << 6) | (0 << 5) | (0 << 4) | (1 << 2) | (1 << 0), SMBUS_IO_BASE + 0xc0 + 16); //REVC_MEMRST_EN=1
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outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 16); //REVC_MEMRST_EN=1
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}
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}
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outb((0 << 7) | (0 << 6) | (0 << 5) | (0 << 4) | (1 << 2) |
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outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 17);
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(0 << 0), SMBUS_IO_BASE + 0xc0 + 17);
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}
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}
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static void memreset(int controllers, const struct mem_controller *ctrl)
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static void memreset(int controllers, const struct mem_controller *ctrl)
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{
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{
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if (is_cpu_pre_c0()) {
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if (is_cpu_pre_c0()) {
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udelay(800);
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udelay(800);
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outb((0<<7)|(0<<6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 17); //REVB_MEMRST_L=1
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outb((0 << 7) | (0 << 6) | (0 << 5) | (0 << 4) | (1 << 2) | (1 << 0), SMBUS_IO_BASE + 0xc0 + 17); //REVB_MEMRST_L=1
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udelay(90);
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udelay(90);
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}
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}
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}
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}
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static unsigned int generate_row(uint8_t node, uint8_t row, uint8_t maxnodes)
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static unsigned int generate_row(uint8_t node, uint8_t row,
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uint8_t maxnodes)
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{
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{
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/* Routing Table Node i
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/* Routing Table Node i
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*
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*
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@ -85,7 +86,7 @@ static unsigned int generate_row(uint8_t node, uint8_t row, uint8_t maxnodes)
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* [3] Route to Link 2
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* [3] Route to Link 2
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*/
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*/
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uint32_t ret=0x00010101; /* default row entry */
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uint32_t ret = 0x00010101; /* default row entry */
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return ret;
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return ret;
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@ -93,9 +94,9 @@ static unsigned int generate_row(uint8_t node, uint8_t row, uint8_t maxnodes)
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static inline void activate_spd_rom(const struct mem_controller *ctrl)
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static inline void activate_spd_rom(const struct mem_controller *ctrl)
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{
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{
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/* nothing to do */
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/* nothing to do */
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}
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}
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static inline int spd_read_byte(unsigned device, unsigned address)
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static inline int spd_read_byte(unsigned device, unsigned address)
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{
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{
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return smbus_read_byte(device, address);
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return smbus_read_byte(device, address);
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@ -113,47 +114,47 @@ static void main(void)
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*/
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*/
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static const struct mem_controller cpu[] = {
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static const struct mem_controller cpu[] = {
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{
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{
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.node_id = 0,
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.node_id = 0,
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.f0 = PCI_DEV(0, 0x18, 0),
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.f0 = PCI_DEV(0, 0x18, 0),
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.f1 = PCI_DEV(0, 0x18, 1),
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.f1 = PCI_DEV(0, 0x18, 1),
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.f2 = PCI_DEV(0, 0x18, 2),
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.f2 = PCI_DEV(0, 0x18, 2),
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.f3 = PCI_DEV(0, 0x18, 3),
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.f3 = PCI_DEV(0, 0x18, 3),
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.channel0 = { (0xa<<3)|0, (0xa<<3)|2, 0, 0 },
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.channel0 = {(0xa << 3) | 0, (0xa << 3) | 2, 0, 0},
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.channel1 = { (0xa<<3)|1, (0xa<<3)|3, 0, 0 },
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.channel1 = {(0xa << 3) | 1, (0xa << 3) | 3, 0, 0},
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},
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},
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};
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};
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int needs_reset;
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int needs_reset;
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enable_lapic();
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enable_lapic();
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init_timer();
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init_timer();
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if (cpu_init_detected()) {
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if (cpu_init_detected()) {
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asm("jmp __cpu_reset");
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asm("jmp __cpu_reset");
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}
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}
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distinguish_cpu_resets();
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distinguish_cpu_resets();
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if (!boot_cpu()) {
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if (!boot_cpu()) {
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stop_this_cpu();
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stop_this_cpu();
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}
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}
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w83627hf_enable_serial(SERIAL_DEV, TTYS0_BASE);
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w83627hf_enable_serial(SERIAL_DEV, TTYS0_BASE);
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uart_init();
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uart_init();
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console_init();
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console_init();
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setup_default_resource_map();
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setup_default_resource_map();
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needs_reset = setup_coherent_ht_domain();
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needs_reset = setup_coherent_ht_domain();
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needs_reset |= ht_setup_chain(PCI_DEV(0, 0x18, 0), 0x80);
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needs_reset |= ht_setup_chain(PCI_DEV(0, 0x18, 0), 0x80);
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if (needs_reset) {
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if (needs_reset) {
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print_info("ht reset -\r\n");
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print_info("ht reset -\r\n");
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soft_reset();
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soft_reset();
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}
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}
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#if 0
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#if 0
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print_pci_devices();
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print_pci_devices();
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#endif
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#endif
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enable_smbus();
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enable_smbus();
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#if 0
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#if 0
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// dump_spd_registers(&cpu[0]);
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// dump_spd_registers(&cpu[0]);
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dump_smbus_registers();
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dump_smbus_registers();
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#endif
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#endif
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memreset_setup();
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memreset_setup();
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sdram_initialize(sizeof(cpu)/sizeof(cpu[0]), cpu);
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sdram_initialize(sizeof(cpu) / sizeof(cpu[0]), cpu);
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#if 0
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#if 0
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dump_pci_devices();
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dump_pci_devices();
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