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Trivial fixes of printk \r\n and white space.

Browse source 
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Myles Watson <mylesgw@gmail.com>


git-svn-id: svn://coreboot.org/repository/coreboot-v3@958 f3766cd6-281f-0410-b1cd-43a5c92072e9
This commit is contained in:
Myles Watson 2008-10-28 17:29:07 +00:00
parent 345f5ac818
commit e7ea68860d
12 changed files with 634 additions and 634 deletions
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38
arch/x86/amd/model_fxx/init_cpus.c
View file

@ -69,7 +69,7 @@ void for_each_ap(unsigned bsp_apicid, unsigned core_range,
nodes = get_nodes();
/* if the get_option fails siblings remain disabled. */
// This sound not be a config option. disable_siblings = !CONFIG_LOGICAL_CPUS;
// This sound not be a config option. disable_siblings = !CONFIG_LOGICAL_CPUS;
//get_option(&disable_siblings, "dual_core");
/* There is an interesting problem in different steppings. See page 373. The interpretation of the
@ -195,7 +195,7 @@ void print_apicid_nodeid_coreid(unsigned apicid, struct node_core_id id,
const char *str)
{
printk(BIOS_DEBUG, "%s --- { APICID = %02x NODEID = %02x COREID = %02x} ---\n",
str, apicid, id.nodeid, id.coreid);
str, apicid, id.nodeid, id.coreid);
}
@ -255,16 +255,16 @@ void disable_cache_as_ram_bsp(void)
{
__asm__ volatile (
// "pushl %eax\n\t"
"pushl %edx\n\t"
"pushl %ecx\n\t"
"pushl %edx\n\t"
"pushl %ecx\n\t"
);
disable_cache_as_ram();
__asm__ volatile (
"popl %ecx\n\t"
"popl %edx\n\t"
// "popl %eax\n\t"
);
__asm__ volatile (
"popl %ecx\n\t"
"popl %edx\n\t"
// "popl %eax\n\t"
);
}
@ -285,7 +285,7 @@ void wait_all_other_cores_started(unsigned bsp_apicid) // all aps other than cor
{
printk(BIOS_DEBUG, "started ap apicid: ");
for_each_ap(bsp_apicid, 2, wait_ap_started, (void *) 0);
printk(BIOS_DEBUG, "\r\n");
printk(BIOS_DEBUG, "\n");
}
void STOP_CAR_AND_CPU(void)
@ -301,8 +301,8 @@ void STOP_CAR_AND_CPU(void)
#if MEM_TRAIN_SEQ == 1
void train_ram_on_node(unsigned nodeid, unsigned coreid,
struct sys_info *sysinfo,
void * retcall);
struct sys_info *sysinfo,
void * retcall);
#endif
/**
@ -330,7 +330,7 @@ void train_ram_on_node(unsigned nodeid, unsigned coreid,
* @returns the BSP APIC ID
*/
unsigned int init_cpus(unsigned cpu_init_detectedx,
struct sys_info *sysinfo)
struct sys_info *sysinfo)
{
unsigned bsp_apicid = 0;
unsigned apicid;
@ -373,7 +373,7 @@ cpu_init_detectedx = 0;
/* enable the local APIC, which we need to do message passing between sockets. */
enable_lapic();
// init_timer(); // We need TMICT to pass msg for FID/VID change
// init_timer(); // We need TMICT to pass msg for FID/VID change
#if (ENABLE_APIC_EXT_ID == 1)
/* we wish to enable extended APIC IDs. We have an APIC ID already which we can
@ -422,15 +422,15 @@ cpu_init_detectedx = 0;
if (cpu_init_detectedx) {
print_apicid_nodeid_coreid(apicid, id,
"\r\n\r\n\r\nINIT detected from ");
printk(BIOS_DEBUG, "\r\nIssuing SOFT_RESET...\r\n");
"\n\n\nINIT detected from ");
printk(BIOS_DEBUG, "\nIssuing SOFT_RESET...\n");
soft_reset();
}
if (id.coreid == 0) {
/* not known what this is yet. */
distinguish_cpu_resets(id.nodeid);
// start_other_core(id.nodeid); // start second core in first cpu, only allowed for nb_cfg_54 is not set
// start_other_core(id.nodeid); // start second core in first cpu, only allowed for nb_cfg_54 is not set
}
//Indicate to other CPUs that our CPU is running.
/* and, again, recall that this is running on all sockets at some point, although it runs at
@ -468,7 +468,7 @@ cpu_init_detectedx = 0;
}
if (timeout) {
printk(BIOS_DEBUG, "while waiting for BSP signal to STOP, timeout in ap 0x%08x\n",
apicid);
apicid);
}
/* indicate that we are in state 44 as well. We are catching up to the BSP. */
// old comment follows -- not sure what this means yet.
@ -523,6 +523,6 @@ void wait_all_core0_started(void)
}
printk(BIOS_DEBUG, "%s%02x", " ", i);
}
printk(BIOS_DEBUG, "\r\n");
printk(BIOS_DEBUG, "\n");
}

8
mainboard/amd/dbm690t/initram.c
View file

@ -127,7 +127,7 @@ int main(void)
*/
bsp_apicid = init_cpus(init_detected, sysinfo);
// dump_mem(DCACHE_RAM_BASE+DCACHE_RAM_SIZE-0x200, DCACHE_RAM_BASE+DCACHE_RAM_SIZE);
// dump_mem(DCACHE_RAM_BASE+DCACHE_RAM_SIZE-0x200, DCACHE_RAM_BASE+DCACHE_RAM_SIZE);
#if 0
dump_pci_device(PCI_DEV(0, 0x18, 0));
@ -176,7 +176,7 @@ int main(void)
// fidvid change will issue one LDTSTOP and the HT change will be effective too
if (needs_reset) {
printk(BIOS_INFO, "ht reset -\r\n");
printk(BIOS_INFO, "ht reset -\n");
// soft_reset_x(sysinfo->sbbusn, sysinfo->sbdn);
soft_reset();
}
@ -192,7 +192,7 @@ int main(void)
//do we need apci timer, tsc...., only debug need it for better output
/* all ap stopped? */
// init_timer(); // Need to use TMICT to synconize FID/VID
// init_timer(); // Need to use TMICT to synconize FID/VID
sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);
@ -201,7 +201,7 @@ int main(void)
#endif
#if 0
// dump_pci_devices();
// dump_pci_devices();
dump_pci_device_index_wait(PCI_DEV(0, 0x18, 2), 0x98);
dump_pci_device_index_wait(PCI_DEV(0, 0x19, 2), 0x98);
#endif

14
mainboard/amd/serengeti/initram.c
View file

@ -59,8 +59,8 @@ static void memreset_setup(void)
{
void memreset_setup_amd8111(u8 data, u16 offset);
//GPIO on amd8111 to enable MEMRST ????
memreset_setup_amd8111((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), 0xc0 + 16); //REVC_MEMRST_EN=1
memreset_setup_amd8111((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), 0xc0 + 17);
memreset_setup_amd8111((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), 0xc0 + 16); //REVC_MEMRST_EN=1
memreset_setup_amd8111((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), 0xc0 + 17);
}
/**
@ -166,7 +166,7 @@ int main(void)
*/
bsp_apicid = init_cpus(init_detected, sysinfo);
// dump_mem(DCACHE_RAM_BASE+DCACHE_RAM_SIZE-0x200, DCACHE_RAM_BASE+DCACHE_RAM_SIZE);
// dump_mem(DCACHE_RAM_BASE+DCACHE_RAM_SIZE-0x200, DCACHE_RAM_BASE+DCACHE_RAM_SIZE);
#if 0
dump_pci_device(PCI_DEV(0, 0x18, 0));
@ -195,7 +195,7 @@ int main(void)
ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn
#if 0
//it your CPU min fid is 1G, you can change HT to 1G and FID to max one time.
//if your CPU min fid is 1G, you can change HT to 1G and FID to max one time.
needs_reset = optimize_link_coherent_ht();
needs_reset |= optimize_link_incoherent_ht(sysinfo);
#endif
@ -220,7 +220,7 @@ int main(void)
// fidvid change will issue one LDTSTOP and the HT change will be effective too
if (needs_reset) {
printk(BIOS_INFO, "ht reset -\r\n");
printk(BIOS_INFO, "ht reset -\n");
soft_reset_x(sysinfo->sbbusn, sysinfo->sbdn);
}
#endif
@ -235,7 +235,7 @@ int main(void)
//do we need apci timer, tsc...., only debug need it for better output
/* all ap stopped? */
// init_timer(); // Need to use TMICT to synconize FID/VID
// init_timer(); // Need to use TMICT to synconize FID/VID
sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);
@ -244,7 +244,7 @@ int main(void)
#endif
#if 0
// dump_pci_devices();
// dump_pci_devices();
dump_pci_device_index_wait(PCI_DEV(0, 0x18, 2), 0x98);
dump_pci_device_index_wait(PCI_DEV(0, 0x19, 2), 0x98);
#endif

2
northbridge/amd/geodelx/raminit.c
View file

@ -84,7 +84,7 @@ void dumplxmsrs(void)
*/
void hcf(void)
{
printk(BIOS_EMERG, "DIE\r\n");
printk(BIOS_EMERG, "DIE\n");
/* This guarantees we flush the UART FIFOs (if any) and also ensures
* that things, in general, keep going so no debug output is lost.

430
northbridge/amd/k8/coherent_ht.c
View file

@ -116,7 +116,7 @@
#endif
#ifndef ENABLE_APIC_EXT_ID
#define ENABLE_APIC_EXT_ID 0
#define ENABLE_APIC_EXT_ID 0
#endif
@ -171,9 +171,9 @@ void enable_apic_ext_id(u8 node)
u32 val;
val = pci_conf1_read_config32(NODE_HT(node), 0x68);
val |= (HTTC_APIC_EXT_SPUR | HTTC_APIC_EXT_ID | HTTC_APIC_EXT_BRD_CST);
pci_conf1_write_config32(NODE_HT(node), 0x68, val);
val = pci_conf1_read_config32(NODE_HT(node), 0x68);
val |= (HTTC_APIC_EXT_SPUR | HTTC_APIC_EXT_ID | HTTC_APIC_EXT_BRD_CST);
pci_conf1_write_config32(NODE_HT(node), 0x68, val);
#endif
}
@ -210,7 +210,7 @@ void enable_routing(u8 node)
val &= ~((1<<1)|(1<<0));
pci_conf1_write_config32(NODE_HT(node), 0x6c, val);
printk(BIOS_SPEW, " done.\r\n");
printk(BIOS_SPEW, " done.\n");
}
void fill_row(u8 node, u8 row, u32 value)
@ -256,7 +256,7 @@ void rename_temp_node(u8 node)
val=pci_conf1_read_config32(NODE_HT(7), 0x60);
val &= (~7); /* clear low bits. */
val |= node; /* new node */
val |= node; /* new node */
pci_conf1_write_config32(NODE_HT(7), 0x60, val);
printk(BIOS_SPEW, " done.\n");
@ -271,7 +271,7 @@ int verify_connection(u8 dest)
* established and actually working by reading the
* remode node's vendor/device id
*/
val = pci_conf1_read_config32(NODE_HT(dest),0);
val = pci_conf1_read_config32(NODE_HT(dest),0);
if(val != 0x11001022)
return 0;
@ -379,27 +379,27 @@ int optimize_connection(u32 node1, u8 link1, u32 node2, u8 link2)
u8 get_linkn_first(u8 byte)
{
if(byte & 0x02) { byte = 0; }
else if(byte & 0x04) { byte = 1; }
else if(byte & 0x08) { byte = 2; }
return byte;
if(byte & 0x02) { byte = 0; }
else if(byte & 0x04) { byte = 1; }
else if(byte & 0x08) { byte = 2; }
return byte;
}
u8 get_linkn_last(u8 byte)
{
if(byte & 0x02) { byte &= 0x0f; byte |= 0x00; }
if(byte & 0x04) { byte &= 0x0f; byte |= 0x10; }
if(byte & 0x08) { byte &= 0x0f; byte |= 0x20; }
return byte>>4;
if(byte & 0x02) { byte &= 0x0f; byte |= 0x00; }
if(byte & 0x04) { byte &= 0x0f; byte |= 0x10; }
if(byte & 0x08) { byte &= 0x0f; byte |= 0x20; }
return byte>>4;
}
u8 get_linkn_last_count(u8 byte)
{
byte &= 0x0f;
if(byte & 0x02) { byte &= 0xcf; byte |= 0x00; byte+=0x40; }
if(byte & 0x04) { byte &= 0xcf; byte |= 0x10; byte+=0x40; }
if(byte & 0x08) { byte &= 0xcf; byte |= 0x20; byte+=0x40; }
return byte>>4;
byte &= 0x0f;
if(byte & 0x02) { byte &= 0xcf; byte |= 0x00; byte+=0x40; }
if(byte & 0x04) { byte &= 0xcf; byte |= 0x10; byte+=0x40; }
if(byte & 0x08) { byte &= 0xcf; byte |= 0x20; byte+=0x40; }
return byte>>4;
}
void setup_row_local(u8 source, u8 row) /* source will be 7 when it is for temp use*/
@ -430,7 +430,7 @@ void setup_row_direct_x(u8 temp, u8 source, u8 dest, u8 linkn)
if(((source &1)!=(dest &1))
#if CONFIG_CROSS_BAR_47_56
&& ( (source<4)||(source>5) ) //(6,7) (7,6) should still be here
//(6,5) (7,4) should be here
//(6,5) (7,4) should be here
#endif
){
val |= (1<<16);
@ -455,25 +455,25 @@ void opt_broadcast_rt(u8 source, u8 dest, u8 kickout) {
}
void opt_broadcast_rt_group(const u8 *conn, int num) {
int i;
int i;
for(i=0; i<num; i+=3) {
opt_broadcast_rt(conn[i], conn[i+1],conn[i+2]);
}
for(i=0; i<num; i+=3) {
opt_broadcast_rt(conn[i], conn[i+1],conn[i+2]);
}
}
void opt_broadcast_rt_plus(u8 source, u8 dest, u8 kickout) {
u32 val;
val = get_row(source, dest);
val += link_connection(source, kickout)<<16;
fill_row(source, dest, val);
u32 val;
val = get_row(source, dest);
val += link_connection(source, kickout)<<16;
fill_row(source, dest, val);
}
void opt_broadcast_rt_plus_group(const u8 *conn, int num) {
int i;
int i;
for(i=0; i<num; i+=3) {
opt_broadcast_rt_plus(conn[i], conn[i+1],conn[i+2]);
}
for(i=0; i<num; i+=3) {
opt_broadcast_rt_plus(conn[i], conn[i+1],conn[i+2]);
}
}
#endif
@ -520,7 +520,7 @@ void setup_remote_node(u8 node)
pci_conf1_write_config32(NODE_MP(7), reg, value);
}
printk(BIOS_SPEW, "done\r\n");
printk(BIOS_SPEW, "done\n");
}
#endif /* CONFIG_MAX_PHYSICAL_CPUS > 1*/
@ -578,7 +578,7 @@ void setup_row_indirect_x(u8 temp, u8 source, u8 dest, u8 gateway, u8 diff)
} else
#endif
if (source < gateway) { // for 5, 4 via 7
val_s-=link_connection(temp, source-2);
val_s-=link_connection(temp, source-2);
} else
#endif
val_s-=link_connection(temp, source+2); /* -up*/
@ -659,7 +659,7 @@ void setup_remote_row_indirect_group(const u8 *conn, int num)
void setup_uniprocessor(void)
{
printk(BIOS_SPEW, "Enabling UP settings\r\n");
printk(BIOS_SPEW, "Enabling UP settings\n");
#if CONFIG_LOGICAL_CPUS==1
unsigned tmp = (pci_conf1_read_config32(NODE_MC(0), 0xe8) >> 12) & 3;
if (tmp>0) return;
@ -865,37 +865,37 @@ unsigned setup_smp4(void)
#if (CONFIG_MAX_PHYSICAL_CPUS > 4) || (CONFIG_MAX_PHYSICAL_CPUS_4_BUT_MORE_INSTALLED == 1)
/* set link from 3 to 5 before enable it*/
val = get_row(7,3);
byte = ((val>>16) & 0xfe) - link_connection(7,2) - link_connection(7,1);
byte = get_linkn_last_count(byte);
if((byte>>2)==1) { /* We should have three coherent links on node 3 for 6p and above*/
byte &= 3; /*bit [3,2] is count-2*/
print_linkn("(3,5) link=", byte);
setup_remote_row_direct(3, 5, byte);
val = get_row(7,3);
byte = ((val>>16) & 0xfe) - link_connection(7,2) - link_connection(7,1);
byte = get_linkn_last_count(byte);
if((byte>>2)==1) { /* We should have three coherent links on node 3 for 6p and above*/
byte &= 3; /*bit [3,2] is count-2*/
print_linkn("(3,5) link=", byte);
setup_remote_row_direct(3, 5, byte);
}
val = get_row(2,2);
byte = ((val>>16) & 0xfe) - link_connection(2,3) - link_connection(2,0);
byte = get_linkn_last_count(byte);
val = get_row(2,2);
byte = ((val>>16) & 0xfe) - link_connection(2,3) - link_connection(2,0);
byte = get_linkn_last_count(byte);
if((byte>>2)==1) { /* We should have three coherent link on node 2 for 6p and above*/
byte &= 3; /* bit [3,2] is count-2*/
print_linkn("(2,4) link=", byte);
setup_row_direct(2, 4, byte);
if((byte>>2)==1) { /* We should have three coherent link on node 2 for 6p and above*/
byte &= 3; /* bit [3,2] is count-2*/
print_linkn("(2,4) link=", byte);
setup_row_direct(2, 4, byte);
}
#endif
//Beside 3, 1 is set, We need to make sure 3, 5 is set already in case has three link in 3
#if !CONFIG_CROSS_BAR_47_56
static const u8 conn4_3[] = {
3,0,
};
static const u8 conn4_3[] = {
3,0,
};
#else
static const u8 conn4_3[] = {
3,0,1,1,
};
static const u8 conn4_3[] = {
3,0,1,1,
};
#endif
setup_remote_row_indirect_group(conn4_3, ARRAY_SIZE(conn4_3));
setup_remote_row_indirect_group(conn4_3, ARRAY_SIZE(conn4_3));
/* ready to enable RT for Node 3 */
rename_temp_node(3);
@ -903,15 +903,15 @@ unsigned setup_smp4(void)
// beside 2, 0 is set, We need to make sure 2, 4 link is set already in case has three link in 2
#if !CONFIG_CROSS_BAR_47_56
static const u8 conn4_2[] = {
2,1,
};
static const u8 conn4_2[] = {
2,1,
};
#else
static const u8 conn4_2[] = {
2,1,0,1,
};
static const u8 conn4_2[] = {
2,1,0,1,
};
#endif
setup_row_indirect_group(conn4_2, ARRAY_SIZE(conn4_2));
setup_row_indirect_group(conn4_2, ARRAY_SIZE(conn4_2));
#if 0
/*We need to do sth to reverse work for setup_temp_row (0,1) (1,3) */
@ -937,24 +937,24 @@ unsigned setup_smp6(void)
nodes=6;
/* Setup and check temporary connection from Node 0 to Node 4 through 2*/
val = get_row(2,2);
byte = ((val>>16) & 0xfe) - link_connection(2,3) - link_connection(2,0);
byte = get_linkn_last_count(byte);
val = get_row(2,2);
byte = ((val>>16) & 0xfe) - link_connection(2,3) - link_connection(2,0);
byte = get_linkn_last_count(byte);
if((byte>>2)==0) { /* We should have three coherent link on node 2 for 6p and above*/
nodes = 4;
return nodes;
}
if((byte>>2)==0) { /* We should have three coherent link on node 2 for 6p and above*/
nodes = 4;
return nodes;
}
/* Setup and check temporary connection from Node 0 to Node 5 through 1, 3*/
/* set link from 3 to 5 before enable it*/
val = get_row(3,3);
byte = ((val>>16) & 0xfe) - link_connection(3,2) - link_connection(3,1);
byte = get_linkn_last_count(byte);
if((byte>>2)==0) { /* We should have three coherent links on node 3 for 6p and above*/
nodes = 4;
return nodes;
}
/* set link from 3 to 5 before enable it*/
val = get_row(3,3);
byte = ((val>>16) & 0xfe) - link_connection(3,2) - link_connection(3,1);
byte = get_linkn_last_count(byte);
if((byte>>2)==0) { /* We should have three coherent links on node 3 for 6p and above*/
nodes = 4;
return nodes;
}
/* We found 6 nodes so far. Now setup all nodes for 6p */
#warning "FIXME we need to find out the correct gateway for 6p"
@ -1054,24 +1054,24 @@ unsigned setup_smp6(void)
setup_remote_row_direct(5,4, byte);
//init 5, 7 here
val = get_row(7,5);
byte = ((val>>16) & 0xfe) - link_connection(7,4) - link_connection(7,3);
byte = get_linkn_last_count(byte);
if((byte>>2)==1) { /* We should have three coherent links on node 5 for 6p and above*/
byte &= 3; /*bit [3,2] is count-2*/
print_linkn("(5,7) link=", byte);
setup_remote_row_direct(5, 7, byte);
val = get_row(7,5);
byte = ((val>>16) & 0xfe) - link_connection(7,4) - link_connection(7,3);
byte = get_linkn_last_count(byte);
if((byte>>2)==1) { /* We should have three coherent links on node 5 for 6p and above*/
byte &= 3; /*bit [3,2] is count-2*/
print_linkn("(5,7) link=", byte);
setup_remote_row_direct(5, 7, byte);
}
//init 4,6 here
val = get_row(4,4);
byte = ((val>>16) & 0xfe) - link_connection(4,5) - link_connection(4,2);
byte = get_linkn_last_count(byte);
val = get_row(4,4);
byte = ((val>>16) & 0xfe) - link_connection(4,5) - link_connection(4,2);
byte = get_linkn_last_count(byte);
if((byte>>2)==1) { /* We should have three coherent link on node 4 for 6p and above*/
byte &= 3; /* bit [3,2] is count-2*/
print_linkn("(4,6) link=", byte);
setup_row_direct(4, 6, byte);
if((byte>>2)==1) { /* We should have three coherent link on node 4 for 6p and above*/
byte &= 3; /* bit [3,2] is count-2*/
print_linkn("(4,6) link=", byte);
setup_row_direct(4, 6, byte);
}
#endif
@ -1145,11 +1145,11 @@ unsigned setup_smp8(void)
byte = ((val>>16) & 0xfe) - link_connection(4,2);
#else
byte = ((val>>16) & 0xfe) - link_connection(4,5) - link_connection(4,2);
byte = get_linkn_last_count(byte); /* Max link to 6*/
if((byte>>2)==0) { /* We should have two or three coherent links on node 4 for 8p*/
nodes = 6;
return nodes;
}
byte = get_linkn_last_count(byte); /* Max link to 6*/
if((byte>>2)==0) { /* We should have two or three coherent links on node 4 for 8p*/
nodes = 6;
return nodes;
}
#endif
#if CONFIG_CROSS_BAR_47_56
@ -1170,13 +1170,13 @@ unsigned setup_smp8(void)
#if !CONFIG_CROSS_BAR_47_56
/* Setup and check temporary connection from Node 0 to Node 7 through 1, 3, 5*/
val = get_row(5,5);
byte = ((val>>16) & 0xfe) - link_connection(5,4) - link_connection(5,3);
byte = get_linkn_last_count(byte);
if((byte>>2)==0) { /* We should have three coherent links on node 5 for 6p and above*/
nodes = 6;
return nodes;
}
val = get_row(5,5);
byte = ((val>>16) & 0xfe) - link_connection(5,4) - link_connection(5,3);
byte = get_linkn_last_count(byte);
if((byte>>2)==0) { /* We should have three coherent links on node 5 for 6p and above*/
nodes = 6;
return nodes;
}
#endif
/* We found 8 nodes so far. Now setup all nodes for 8p */
@ -1231,53 +1231,53 @@ unsigned setup_smp8(void)
#if CONFIG_CROSS_BAR_47_56
//init 5, 6 here
/* here init 5, 6 */
/* Setup and check temporary connection from Node 0 to Node 5 through 1, 3, 5*/
val = get_row(5,5);
byte = ((val>>16) & 0xfe) - link_connection(5,3);
/* here init 5, 6 */
/* Setup and check temporary connection from Node 0 to Node 5 through 1, 3, 5*/
val = get_row(5,5);
byte = ((val>>16) & 0xfe) - link_connection(5,3);
#if TRY_HIGH_FIRST == 1
byte = get_linkn_first(byte);
#else
byte = get_linkn_last(byte);
byte = get_linkn_last(byte);
#endif
print_linkn("(5,6) link=", byte);
setup_row_direct(5, 6, byte);
print_linkn("(5,6) link=", byte);
setup_row_direct(5, 6, byte);
setup_temp_row(0,1); /* temp. link between nodes 0 and 1 */
for(byte=0; byte<4; byte+=2) {
setup_temp_row(byte+1,byte+3);
}
setup_temp_row(0,1); /* temp. link between nodes 0 and 1 */
for(byte=0; byte<4; byte+=2) {
setup_temp_row(byte+1,byte+3);
}
setup_temp_row(5,6);
verify_connection(7);
verify_connection(7);
val = get_row(7,6); // to chect it if it is node6 before renaming
if( (val>>16) == 1) { // it is real node 7 so swap it
/* We need to recompute link to 6 */
val = get_row(5,5);
byte = ((val>>16) & 0xfe) - link_connection(5,3);
/* We need to recompute link to 6 */
val = get_row(5,5);
byte = ((val>>16) & 0xfe) - link_connection(5,3);
#if TRY_HIGH_FIRST == 1
byte = get_linkn_first(byte);
byte = get_linkn_first(byte);
#else
byte = get_linkn_last(byte);
byte = get_linkn_last(byte);
#endif
print_linkn("\t-->(5,6) link=", byte);
setup_row_direct(5, 6, byte);
print_linkn("\t-->(5,6) link=", byte);
setup_row_direct(5, 6, byte);
#if 0
setup_temp_row(0,1); /* temp. link between nodes 0 and 1 */
for(byte=0; byte<4; byte+=2) {
setup_temp_row(byte+1,byte+3);
}
setup_temp_row(0,1); /* temp. link between nodes 0 and 1 */
for(byte=0; byte<4; byte+=2) {
setup_temp_row(byte+1,byte+3);
}
#endif
setup_temp_row(5,6);
verify_connection(7);
verify_connection(7);
}
val = pci_conf1_read_config32(NODE_HT(7), 0x6c);
byte = (val>>2) & 0x3; /* get default link on 7 to 5*/
print_linkn("(6,5) link=", byte);
setup_remote_row_direct(6, 5, byte);
/*Till now 56, 65 done */
val = pci_conf1_read_config32(NODE_HT(7), 0x6c);
byte = (val>>2) & 0x3; /* get default link on 7 to 5*/
print_linkn("(6,5) link=", byte);
setup_remote_row_direct(6, 5, byte);
/*Till now 56, 65 done */
#endif
rename_temp_node(6);
@ -1298,18 +1298,18 @@ unsigned setup_smp8(void)
setup_remote_row_direct(7, 5, byte);
#else
val = get_row(4,4);
byte = ((val>>16) & 0xfe) - link_connection(4,2) - link_connection(4,6);
byte = get_linkn_first(byte);
print_linkn("(4,7) link=", byte);
setup_row_direct(4, 7, byte);
val = get_row(4,4);
byte = ((val>>16) & 0xfe) - link_connection(4,2) - link_connection(4,6);
byte = get_linkn_first(byte);
print_linkn("(4,7) link=", byte);
setup_row_direct(4, 7, byte);
/* Setup and check temporary connection from Node 0 to Node 7 through 2, and 4*/
/* Setup and check temporary connection from Node 0 to Node 7 through 2, and 4*/
for(byte=0; byte<4; byte+=2) {
setup_temp_row(byte,byte+2);
}
verify_connection(7);
verify_connection(7);
val = pci_conf1_read_config32(NODE_HT(7), 0x6c);
byte = (val>>2) & 0x3; /* get default link on 7 to 4*/
@ -1387,25 +1387,25 @@ unsigned setup_smp8(void)
#else
4, 5, 6, 1,
5, 4, 7, 1,
4, 5, 6, 1,
5, 4, 7, 1,
6, 1, 5, 0, // or 4, 1
6, 2, 4, 0,
6, 3, 5, 0, // or 4, 1
6, 1, 5, 0, // or 4, 1
6, 2, 4, 0,
6, 3, 5, 0, // or 4, 1
7, 0, 4, 0, // or 5, 1
7, 1, 5, 0,
7, 2, 4, 0, // or 5, 1
7, 3, 5, 0,
7, 0, 4, 0, // or 5, 1
7, 1, 5, 0,
7, 2, 4, 0, // or 5, 1
7, 3, 5, 0,
0, 7, 2, 0, /* restore it*/
1, 7, 3, 0,
2, 7, 4, 1,
3, 7, 5, 0,
2, 5, 4, 1, /* reset it */
3, 4, 5, 1,
2, 5, 4, 1, /* reset it */
3, 4, 5, 1,
4, 1, 2, 1, /* reset it */
4, 3, 2, 1,
@ -1419,12 +1419,12 @@ unsigned setup_smp8(void)
setup_row_indirect_group(conn8_3, ARRAY_SIZE(conn8_3));
#if CONFIG_CROSS_BAR_47_56
/* for 47, 56, 57, 75, 46, 64 we need to substract another link to
6, 7, 6, 6, 7, 7 */
static const u8 conn8_4[] = {
/* for 47, 56, 57, 75, 46, 64 we need to substract another link to
6, 7, 6, 6, 7, 7 */
static const u8 conn8_4[] = {
//direct
4, 7, 6,
5, 6, 7,
4, 7, 6,
5, 6, 7,
5, 7, 6,
7, 5, 6,
4, 6, 7,
@ -1455,17 +1455,17 @@ unsigned setup_smp8(void)
7, 2, 6, // needed for via 4
7, 2, 5, //???
7, 3, 6,
};
};
opt_broadcast_rt_group(conn8_4, ARRAY_SIZE(conn8_4));
opt_broadcast_rt_group(conn8_4, ARRAY_SIZE(conn8_4));
static const u8 conn8_5[] = {
2, 7, 0,
static const u8 conn8_5[] = {
2, 7, 0,
3, 6, 1,
};
3, 6, 1,
};
opt_broadcast_rt_plus_group(conn8_5, ARRAY_SIZE(conn8_5));
opt_broadcast_rt_plus_group(conn8_5, ARRAY_SIZE(conn8_5));
#endif
@ -1485,7 +1485,7 @@ unsigned setup_smp(void)
{
unsigned nodes;
printk(BIOS_SPEW, "Enabling SMP settings\r\n");
printk(BIOS_SPEW, "Enabling SMP settings\n");
nodes = setup_smp2();
#if CONFIG_MAX_PHYSICAL_CPUS > 2
@ -1503,7 +1503,7 @@ unsigned setup_smp(void)
nodes = setup_smp8();
#endif
printk(BIOS_DEBUG,"%02x nodes initialized.\r\n", nodes);
printk(BIOS_DEBUG,"%02x nodes initialized.\n", nodes);
return nodes;
}
@ -1522,14 +1522,14 @@ unsigned verify_mp_capabilities(unsigned nodes)
#if CONFIG_MAX_PHYSICAL_CPUS > 2
case 0x02: /* MPCap */
if(nodes > 2) {
print_err("Going back to DP\r\n");
print_err("Going back to DP\n");
return 2;
}
break;
#endif
case 0x00: /* Non SMP */
if(nodes >1 ) {
print_err("Going back to UP\r\n");
print_err("Going back to UP\n");
return 1;
}
break;
@ -1606,7 +1606,7 @@ void coherent_ht_finalize(unsigned nodes)
* registers on Hammer A0 revision.
*/
printk(BIOS_SPEW, "coherent_ht_finalize\r\n");
printk(BIOS_SPEW, "coherent_ht_finalize\n");
for (node = 0; node < nodes; node++) {
u32 dev;
u32 val;
@ -1637,7 +1637,7 @@ void coherent_ht_finalize(unsigned nodes)
}
printk(BIOS_SPEW, "done\r\n");
printk(BIOS_SPEW, "done\n");
}
int apply_cpu_errata_fixes(unsigned int nodes)
@ -1686,65 +1686,65 @@ int optimize_link_read_pointers(unsigned nodes)
int optimize_link_coherent_ht(void)
{
int needs_reset = 0;
int needs_reset = 0;
unsigned nodes;
unsigned nodes;
nodes = get_nodes();
nodes = get_nodes();
#if CONFIG_MAX_PHYSICAL_CPUS > 1
if(nodes>1) {
needs_reset |= optimize_connection(
NODE_HT(0), 0x80 + link_to_register(link_connection(0,1)),
NODE_HT(1), 0x80 + link_to_register(link_connection(1,0)) );
}
if(nodes>1) {
needs_reset |= optimize_connection(
NODE_HT(0), 0x80 + link_to_register(link_connection(0,1)),
NODE_HT(1), 0x80 + link_to_register(link_connection(1,0)) );
}
#if CONFIG_MAX_PHYSICAL_CPUS > 2
if(nodes>2) {
/* optimize physical connections - by LYH */
static const u8 opt_conn4[] = {
0,2,
1,3,
2,3,
};
needs_reset |= optimize_connection_group(opt_conn4, ARRAY_SIZE(opt_conn4));
}
if(nodes>2) {
/* optimize physical connections - by LYH */
static const u8 opt_conn4[] = {
0,2,
1,3,
2,3,
};
needs_reset |= optimize_connection_group(opt_conn4, ARRAY_SIZE(opt_conn4));
}
#endif
#if CONFIG_MAX_PHYSICAL_CPUS > 4
if(nodes>4) {
static const u8 opt_conn6[] ={
2, 4,
3, 5,
#if !CONFIG_CROSS_BAR_47_56
4, 5,
#endif
};
needs_reset |= optimize_connection_group(opt_conn6, ARRAY_SIZE(opt_conn6));
}
if(nodes>4) {
static const u8 opt_conn6[] ={
2, 4,
3, 5,
#if !CONFIG_CROSS_BAR_47_56
4, 5,
#endif
};
needs_reset |= optimize_connection_group(opt_conn6, ARRAY_SIZE(opt_conn6));
}
#endif
#if CONFIG_MAX_PHYSICAL_CPUS > 6
if(nodes>6) {
static const u8 opt_conn8[] ={
4, 6,
#if CONFIG_CROSS_BAR_47_56
4, 7,
5, 6,
#endif
5, 7,
6, 7,
};
needs_reset |= optimize_connection_group(opt_conn8, ARRAY_SIZE(opt_conn8));
}
if(nodes>6) {
static const u8 opt_conn8[] ={
4, 6,
#if CONFIG_CROSS_BAR_47_56
4, 7,
5, 6,
#endif
5, 7,
6, 7,
};
needs_reset |= optimize_connection_group(opt_conn8, ARRAY_SIZE(opt_conn8));
}
#endif
#endif
needs_reset |= apply_cpu_errata_fixes(nodes);
needs_reset |= optimize_link_read_pointers(nodes);
needs_reset |= apply_cpu_errata_fixes(nodes);
needs_reset |= optimize_link_read_pointers(nodes);
return needs_reset;
return needs_reset;
}
void setup_coherent_ht_domain(void)
@ -1755,9 +1755,9 @@ void setup_coherent_ht_domain(void)
enable_bsp_routing();
#if CONFIG_MAX_PHYSICAL_CPUS > 1
nodes = setup_smp();
nodes = verify_mp_capabilities(nodes);
clear_dead_routes(nodes);
nodes = setup_smp();
nodes = verify_mp_capabilities(nodes);
clear_dead_routes(nodes);
#endif
if (nodes == 1) {

2
northbridge/amd/k8/cpu.c
View file

@ -148,7 +148,7 @@ static unsigned int cpu_bus_scan(struct device * dev, unsigned int max)
e0_later_single_core = 0;
}
if(e0_later_single_core) {
printk(BIOS_DEBUG, "\tFound Rev E or Rev F later single core\r\n");
printk(BIOS_DEBUG, "\tFound Rev E or Rev F later single core\n");
j=1;
}

6
southbridge/amd/amd8111/stage1_smbus.c
View file

@ -42,7 +42,7 @@ void enable_smbus(void)
/* Yes, the ACPI device controls the SMBUS. */
if (!pci_conf1_find_on_bus(0, PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8111_ACPI, &dev)){
die("SMBUS controller not found\r\n");
die("SMBUS controller not found\n");
}
pci_conf1_write_config32(dev, 0x58, SMBUS_IO_BASE | 1);
@ -56,7 +56,7 @@ void enable_smbus(void)
/* clear any lingering errors, so the transaction will run */
outw(inw(SMBUS_IO_BASE + SMBGSTATUS), SMBUS_IO_BASE + SMBGSTATUS);
printk(BIOS_SPEW, "SMBus controller enabled\r\n");
printk(BIOS_SPEW, "SMBus controller enabled\n");
}
int smbus_wait_until_ready(u16 smbus_io_base)
@ -302,7 +302,7 @@ int smbus_write_byte(u16 device, u16 address, u8 val)
*/
u8 spd_read_byte(u16 device, u8 address)
{
return smbus_read_byte(device, address);
return smbus_read_byte(device, address);
}
/**

10
southbridge/amd/sb600/stage1.c
View file

@ -69,7 +69,7 @@ static u8 get_sb600_revision(void)
{
u32 dev;
if (!pci_conf1_find_device(PCI_VENDOR_ID_ATI, 0x4385, &dev)){
die("SMBUS controller not found\r\n");
die("SMBUS controller not found\n");
}
return pci_conf1_read_config8(dev, 0x08);
}
@ -277,10 +277,10 @@ static void sb600_devices_por_init(void)
/* SMBus Device, BDF:0-20-0 */
printk(BIOS_INFO, "sb600_devices_por_init(): SMBus Device, BDF:0-20-0\n");
if (!pci_conf1_find_device(PCI_VENDOR_ID_ATI, 0x4385, &dev)){
die("SMBUS controller not found\r\n");
die("SMBUS controller not found\n");
}
printk(BIOS_INFO, "SMBus controller enabled, sb revision is 0x%x\r\n",
get_sb600_revision());
printk(BIOS_INFO, "SMBus controller enabled, sb revision is 0x%x\n",
get_sb600_revision());
/* sbPorAtStartOfTblCfg */
/* Set A-Link bridge access address. This address is set at device 14h, function 0, register 0xf0.
@ -402,7 +402,7 @@ static void sb600_devices_por_init(void)
pci_conf1_write_config8(dev, 0x7C, 0x05);
/* P2P Bridge, BDF:0-20-4, the configuration of the registers in this dev are copied from CIM,
* TODO: I don't know what are their mean? */
* TODO: I don't know what these mean? */
printk(BIOS_INFO, "sb600_devices_por_init(): P2P Bridge, BDF:0-20-4\n");
pci_conf1_find_device(PCI_VENDOR_ID_ATI, 0x4384, &dev);
/* I don't know why CIM tried to write into a read-only reg! */

2
southbridge/nvidia/mcp55/stage1.c
View file

@ -436,7 +436,7 @@ unsigned int get_sbdn(unsigned int bus)
*/
u32 bdf;
if (!pci_conf1_find_device(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_MCP55_HT, &bdf)) {
die("PCI_DEVICE_ID_NVIDIA_MCP55_HT not found\r\n");
die("PCI_DEVICE_ID_NVIDIA_MCP55_HT not found\n");
}
return (bdf>>15) & 0x1f;

4
southbridge/nvidia/mcp55/stage1_smbus.c
View file

@ -192,7 +192,7 @@ void enable_smbus(void)
{
u32 bdf;
if (!pci_conf1_find_device(0x10de, 0x0368, &bdf)) {
die("SMBUS controller not found\r\n");
die("SMBUS controller not found\n");
}
printk(BIOS_DEBUG, "SMBus controller enabled\n");
@ -261,6 +261,6 @@ u8 smbusx_write_byte(u8 smb_index, u8 device, u8 address, u8 val)
*/
u8 spd_read_byte(u16 device, u8 address)
{
return smbus_read_byte(device, address);
return smbus_read_byte(device, address);
}

10
superio/ite/it8716f/superio.c
View file

@ -74,14 +74,14 @@ static void init_ec(u16 base)
/* Read out current value of FAN_CTL control register (0x14). */
value = pnp_read_index(base, 0x14);
printk(BIOS_DEBUG, "FAN_CTL: reg = 0x%04x, read value = 0x%02x\r\n",
base + 0x14, value);
printk(BIOS_DEBUG, "FAN_CTL: reg = 0x%04x, read value = 0x%02x\n",
base + 0x14, value);
/* Set FAN_CTL control register (0x14) polarity to high, and
activate fans 1, 2 and 3. */
* activate fans 1, 2 and 3. */
pnp_write_index(base, 0x14, value | 0x87);
printk(BIOS_DEBUG, "FAN_CTL: reg = 0x%04x, writing value = 0x%02x\r\n",
base + 0x14, value | 0x87);
printk(BIOS_DEBUG, "FAN_CTL: reg = 0x%04x, writing value = 0x%02x\n",
base + 0x14, value | 0x87);
}
#endif

96
superio/winbond/w83627hf/superio.c
View file

@ -36,25 +36,25 @@
static void pnp_enter_ext_func_mode(struct device * dev)
{
outb(0x87, dev->path.pnp.port);
outb(0x87, dev->path.pnp.port);
outb(0x87, dev->path.pnp.port);
outb(0x87, dev->path.pnp.port);
}
static void pnp_exit_ext_func_mode(struct device * dev)
{
outb(0xaa, dev->path.pnp.port);
outb(0xaa, dev->path.pnp.port);
}
static void pnp_write_index(u16 port_base, u8 reg, u8 value)
{
outb(reg, port_base);
outb(value, port_base + 1);
outb(reg, port_base);
outb(value, port_base + 1);
}
static u8 pnp_read_index(u16 port_base, u8 reg)
{
outb(reg, port_base);
return inb(port_base + 1);
outb(reg, port_base);
return inb(port_base + 1);
}
static void enable_hwm_smbus(struct device * dev) {
@ -80,7 +80,7 @@ static void init_acpi(struct device * dev)
value |= (1<<5);
}
pnp_write_config(dev, 0xE4, value);
pnp_exit_ext_func_mode(dev);
pnp_exit_ext_func_mode(dev);
}
static void init_hwm(u16 base)
@ -90,14 +90,14 @@ static void init_hwm(u16 base)
unsigned hwm_reg_values[] = {
/* reg, mask, data */
0x40, 0xff, 0x81, /* start HWM */
0x48, 0xaa, 0x2a, /* set SMBus base to 0x54>>1 */
0x4a, 0x21, 0x21, /* set T2 SMBus base to 0x92>>1 and T3 SMBus base to 0x94>>1 */
0x4e, 0x80, 0x00,
0x43, 0x00, 0xff,
0x44, 0x00, 0x3f,
0x4c, 0xbf, 0x18,
0x4d, 0xff, 0x80 /* turn off beep */
0x40, 0xff, 0x81, /* start HWM */
0x48, 0xaa, 0x2a, /* set SMBus base to 0x54>>1 */
0x4a, 0x21, 0x21, /* set T2 SMBus base to 0x92>>1 and T3 SMBus base to 0x94>>1 */
0x4e, 0x80, 0x00,
0x43, 0x00, 0xff,
0x44, 0x00, 0x3f,
0x4c, 0xbf, 0x18,
0x4d, 0xff, 0x80 /* turn off beep */
};
@ -107,7 +107,7 @@ static void init_hwm(u16 base)
value &= 0xff & hwm_reg_values[i+1];
value |= 0xff & hwm_reg_values[i+2];
printk(BIOS_SPEW, "base = 0x%04x, reg = 0x%02x, value = 0x%02x\r\n", base, reg,value);
printk(BIOS_SPEW, "base = 0x%04x, reg = 0x%02x, value = 0x%02x\n", base, reg,value);
pnp_write_index(base, reg, value);
}
@ -144,14 +144,14 @@ static void w83627hf_init(struct device * dev)
res1 = find_resource(dev, PNP_IDX_IO1);
init_pc_keyboard(res0->base, res1->base, &keyboard);
break;
case W83627HF_HWM:
res0 = find_resource(dev, PNP_IDX_IO0);
case W83627HF_HWM:
res0 = find_resource(dev, PNP_IDX_IO0);
#define HWM_INDEX_PORT 5
init_hwm(res0->base + HWM_INDEX_PORT);
break;
case W83627HF_ACPI:
init_acpi(dev);
break;
init_hwm(res0->base + HWM_INDEX_PORT);
break;
case W83627HF_ACPI:
init_acpi(dev);
break;
}
}
@ -159,40 +159,40 @@ void w83627hf_pnp_set_resources(struct device * dev)
{
pnp_enter_ext_func_mode(dev);
pnp_set_resources(dev);
pnp_exit_ext_func_mode(dev);
pnp_exit_ext_func_mode(dev);
}
void w83627hf_pnp_enable_resources(struct device * dev)
{
pnp_enter_ext_func_mode(dev);
pnp_enter_ext_func_mode(dev);
pnp_enable_resources(dev);
switch(dev->path.pnp.device) {
switch(dev->path.pnp.device) {
case W83627HF_HWM:
printk(BIOS_DEBUG, "w83627hf hwm smbus enabled\n");
enable_hwm_smbus(dev);
break;
}
pnp_exit_ext_func_mode(dev);
pnp_exit_ext_func_mode(dev);
}
void w83627hf_pnp_enable(struct device * dev)
{
if (!dev->enabled) {
pnp_enter_ext_func_mode(dev);
if (!dev->enabled) {
pnp_enter_ext_func_mode(dev);
pnp_set_logical_device(dev);
pnp_set_enable(dev, 0);
pnp_set_logical_device(dev);
pnp_set_enable(dev, 0);
pnp_exit_ext_func_mode(dev);
}
pnp_exit_ext_func_mode(dev);
}
}
static void phase3_chip_setup_dev(struct device *dev);
struct device_operations w83627hf_ops = {
.phase3_chip_setup_dev = phase3_chip_setup_dev,
.phase3_enable = w83627hf_pnp_enable_resources,
.phase3_chip_setup_dev = phase3_chip_setup_dev,
.phase3_enable = w83627hf_pnp_enable_resources,
.phase4_read_resources = pnp_read_resources,
.phase4_set_resources = w83627hf_pnp_set_resources,
.phase5_enable_resources = w83627hf_pnp_enable,
@ -200,18 +200,18 @@ struct device_operations w83627hf_ops = {
};
static struct pnp_info pnp_dev_info[] = {
{ &w83627hf_ops, W83627HF_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x07f8, 0}, },
{ &w83627hf_ops, W83627HF_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x07f8, 0}, },
{ &w83627hf_ops, W83627HF_SP1, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, },
{ &w83627hf_ops, W83627HF_SP2, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, },
// No 4 { 0,},
{ &w83627hf_ops, W83627HF_KBC, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_IRQ1, { 0x7ff, 0 }, { 0x7ff, 0x4}, },
{ &w83627hf_ops, W83627HF_CIR, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, },
{ &w83627hf_ops, W83627HF_GAME_MIDI_GPIO1, PNP_IO0 | PNP_IO1 | PNP_IRQ0, { 0x7ff, 0 }, {0x7fe, 0x4}, },
{ &w83627hf_ops, W83627HF_GPIO2, },
{ &w83627hf_ops, W83627HF_GPIO3, },
{ &w83627hf_ops, W83627HF_ACPI, },
{ &w83627hf_ops, W83627HF_HWM, PNP_IO0 | PNP_IRQ0, { 0xff8, 0 }, },
{ &w83627hf_ops, W83627HF_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x07f8, 0}, },
{ &w83627hf_ops, W83627HF_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x07f8, 0}, },
{ &w83627hf_ops, W83627HF_SP1, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, },
{ &w83627hf_ops, W83627HF_SP2, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, },
// No 4 { 0,},
{ &w83627hf_ops, W83627HF_KBC, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_IRQ1, { 0x7ff, 0 }, { 0x7ff, 0x4}, },
{ &w83627hf_ops, W83627HF_CIR, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, },
{ &w83627hf_ops, W83627HF_GAME_MIDI_GPIO1, PNP_IO0 | PNP_IO1 | PNP_IRQ0, { 0x7ff, 0 }, {0x7fe, 0x4}, },
{ &w83627hf_ops, W83627HF_GPIO2, },
{ &w83627hf_ops, W83627HF_GPIO3, },
{ &w83627hf_ops, W83627HF_ACPI, },
{ &w83627hf_ops, W83627HF_HWM, PNP_IO0 | PNP_IRQ0, { 0xff8, 0 }, },
};