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Trivial fixes of printk \r\n and white space.

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Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Myles Watson <mylesgw@gmail.com>


git-svn-id: svn://coreboot.org/repository/coreboot-v3@958 f3766cd6-281f-0410-b1cd-43a5c92072e9
This commit is contained in:
Myles Watson 2008-10-28 17:29:07 +00:00
parent 345f5ac818
commit e7ea68860d
12 changed files with 634 additions and 634 deletions
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8
arch/x86/amd/model_fxx/init_cpus.c
View file

@ -285,7 +285,7 @@ void wait_all_other_cores_started(unsigned bsp_apicid) // all aps other than cor
{ {
printk(BIOS_DEBUG, "started ap apicid: "); printk(BIOS_DEBUG, "started ap apicid: ");
for_each_ap(bsp_apicid, 2, wait_ap_started, (void *) 0); for_each_ap(bsp_apicid, 2, wait_ap_started, (void *) 0);
printk(BIOS_DEBUG, "\r\n"); printk(BIOS_DEBUG, "\n");
} }
void STOP_CAR_AND_CPU(void) void STOP_CAR_AND_CPU(void)
@ -422,8 +422,8 @@ cpu_init_detectedx = 0;
if (cpu_init_detectedx) { if (cpu_init_detectedx) {
print_apicid_nodeid_coreid(apicid, id, print_apicid_nodeid_coreid(apicid, id,
"\r\n\r\n\r\nINIT detected from "); "\n\n\nINIT detected from ");
printk(BIOS_DEBUG, "\r\nIssuing SOFT_RESET...\r\n"); printk(BIOS_DEBUG, "\nIssuing SOFT_RESET...\n");
soft_reset(); soft_reset();
} }
@ -523,6 +523,6 @@ void wait_all_core0_started(void)
} }
printk(BIOS_DEBUG, "%s%02x", " ", i); printk(BIOS_DEBUG, "%s%02x", " ", i);
} }
printk(BIOS_DEBUG, "\r\n"); printk(BIOS_DEBUG, "\n");
} }

2
mainboard/amd/dbm690t/initram.c
View file

@ -176,7 +176,7 @@ int main(void)
// fidvid change will issue one LDTSTOP and the HT change will be effective too // fidvid change will issue one LDTSTOP and the HT change will be effective too
if (needs_reset) { if (needs_reset) {
printk(BIOS_INFO, "ht reset -\r\n"); printk(BIOS_INFO, "ht reset -\n");
// soft_reset_x(sysinfo->sbbusn, sysinfo->sbdn); // soft_reset_x(sysinfo->sbbusn, sysinfo->sbdn);
soft_reset(); soft_reset();
} }

4
mainboard/amd/serengeti/initram.c
View file

@ -195,7 +195,7 @@ int main(void)
ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn
#if 0 #if 0
//it your CPU min fid is 1G, you can change HT to 1G and FID to max one time. //if your CPU min fid is 1G, you can change HT to 1G and FID to max one time.
needs_reset = optimize_link_coherent_ht(); needs_reset = optimize_link_coherent_ht();
needs_reset |= optimize_link_incoherent_ht(sysinfo); needs_reset |= optimize_link_incoherent_ht(sysinfo);
#endif #endif
@ -220,7 +220,7 @@ int main(void)
// fidvid change will issue one LDTSTOP and the HT change will be effective too // fidvid change will issue one LDTSTOP and the HT change will be effective too
if (needs_reset) { if (needs_reset) {
printk(BIOS_INFO, "ht reset -\r\n"); printk(BIOS_INFO, "ht reset -\n");
soft_reset_x(sysinfo->sbbusn, sysinfo->sbdn); soft_reset_x(sysinfo->sbbusn, sysinfo->sbdn);
} }
#endif #endif

2
northbridge/amd/geodelx/raminit.c
View file

@ -84,7 +84,7 @@ void dumplxmsrs(void)
*/ */
void hcf(void) void hcf(void)
{ {
printk(BIOS_EMERG, "DIE\r\n"); printk(BIOS_EMERG, "DIE\n");
/* This guarantees we flush the UART FIFOs (if any) and also ensures /* This guarantees we flush the UART FIFOs (if any) and also ensures
* that things, in general, keep going so no debug output is lost. * that things, in general, keep going so no debug output is lost.

18
northbridge/amd/k8/coherent_ht.c
View file

@ -210,7 +210,7 @@ void enable_routing(u8 node)
val &= ~((1<<1)|(1<<0)); val &= ~((1<<1)|(1<<0));
pci_conf1_write_config32(NODE_HT(node), 0x6c, val); pci_conf1_write_config32(NODE_HT(node), 0x6c, val);
printk(BIOS_SPEW, " done.\r\n"); printk(BIOS_SPEW, " done.\n");
} }
void fill_row(u8 node, u8 row, u32 value) void fill_row(u8 node, u8 row, u32 value)
@ -520,7 +520,7 @@ void setup_remote_node(u8 node)
pci_conf1_write_config32(NODE_MP(7), reg, value); pci_conf1_write_config32(NODE_MP(7), reg, value);
} }
printk(BIOS_SPEW, "done\r\n"); printk(BIOS_SPEW, "done\n");
} }
#endif /* CONFIG_MAX_PHYSICAL_CPUS > 1*/ #endif /* CONFIG_MAX_PHYSICAL_CPUS > 1*/
@ -659,7 +659,7 @@ void setup_remote_row_indirect_group(const u8 *conn, int num)
void setup_uniprocessor(void) void setup_uniprocessor(void)
{ {
printk(BIOS_SPEW, "Enabling UP settings\r\n"); printk(BIOS_SPEW, "Enabling UP settings\n");
#if CONFIG_LOGICAL_CPUS==1 #if CONFIG_LOGICAL_CPUS==1
unsigned tmp = (pci_conf1_read_config32(NODE_MC(0), 0xe8) >> 12) & 3; unsigned tmp = (pci_conf1_read_config32(NODE_MC(0), 0xe8) >> 12) & 3;
if (tmp>0) return; if (tmp>0) return;
@ -1485,7 +1485,7 @@ unsigned setup_smp(void)
{ {
unsigned nodes; unsigned nodes;
printk(BIOS_SPEW, "Enabling SMP settings\r\n"); printk(BIOS_SPEW, "Enabling SMP settings\n");
nodes = setup_smp2(); nodes = setup_smp2();
#if CONFIG_MAX_PHYSICAL_CPUS > 2 #if CONFIG_MAX_PHYSICAL_CPUS > 2
@ -1503,7 +1503,7 @@ unsigned setup_smp(void)
nodes = setup_smp8(); nodes = setup_smp8();
#endif #endif
printk(BIOS_DEBUG,"%02x nodes initialized.\r\n", nodes); printk(BIOS_DEBUG,"%02x nodes initialized.\n", nodes);
return nodes; return nodes;
} }
@ -1522,14 +1522,14 @@ unsigned verify_mp_capabilities(unsigned nodes)
#if CONFIG_MAX_PHYSICAL_CPUS > 2 #if CONFIG_MAX_PHYSICAL_CPUS > 2
case 0x02: /* MPCap */ case 0x02: /* MPCap */
if(nodes > 2) { if(nodes > 2) {
print_err("Going back to DP\r\n"); print_err("Going back to DP\n");
return 2; return 2;
} }
break; break;
#endif #endif
case 0x00: /* Non SMP */ case 0x00: /* Non SMP */
if(nodes >1 ) { if(nodes >1 ) {
print_err("Going back to UP\r\n"); print_err("Going back to UP\n");
return 1; return 1;
} }
break; break;
@ -1606,7 +1606,7 @@ void coherent_ht_finalize(unsigned nodes)
* registers on Hammer A0 revision. * registers on Hammer A0 revision.
*/ */
printk(BIOS_SPEW, "coherent_ht_finalize\r\n"); printk(BIOS_SPEW, "coherent_ht_finalize\n");
for (node = 0; node < nodes; node++) { for (node = 0; node < nodes; node++) {
u32 dev; u32 dev;
u32 val; u32 val;
@ -1637,7 +1637,7 @@ void coherent_ht_finalize(unsigned nodes)
} }
printk(BIOS_SPEW, "done\r\n"); printk(BIOS_SPEW, "done\n");
} }
int apply_cpu_errata_fixes(unsigned int nodes) int apply_cpu_errata_fixes(unsigned int nodes)

2
northbridge/amd/k8/cpu.c
View file

@ -148,7 +148,7 @@ static unsigned int cpu_bus_scan(struct device * dev, unsigned int max)
e0_later_single_core = 0; e0_later_single_core = 0;
} }
if(e0_later_single_core) { if(e0_later_single_core) {
printk(BIOS_DEBUG, "\tFound Rev E or Rev F later single core\r\n"); printk(BIOS_DEBUG, "\tFound Rev E or Rev F later single core\n");
j=1; j=1;
} }

4
southbridge/amd/amd8111/stage1_smbus.c
View file

@ -42,7 +42,7 @@ void enable_smbus(void)
/* Yes, the ACPI device controls the SMBUS. */ /* Yes, the ACPI device controls the SMBUS. */
if (!pci_conf1_find_on_bus(0, PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8111_ACPI, &dev)){ if (!pci_conf1_find_on_bus(0, PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8111_ACPI, &dev)){
die("SMBUS controller not found\r\n"); die("SMBUS controller not found\n");
} }
pci_conf1_write_config32(dev, 0x58, SMBUS_IO_BASE | 1); pci_conf1_write_config32(dev, 0x58, SMBUS_IO_BASE | 1);
@ -56,7 +56,7 @@ void enable_smbus(void)
/* clear any lingering errors, so the transaction will run */ /* clear any lingering errors, so the transaction will run */
outw(inw(SMBUS_IO_BASE + SMBGSTATUS), SMBUS_IO_BASE + SMBGSTATUS); outw(inw(SMBUS_IO_BASE + SMBGSTATUS), SMBUS_IO_BASE + SMBGSTATUS);
printk(BIOS_SPEW, "SMBus controller enabled\r\n"); printk(BIOS_SPEW, "SMBus controller enabled\n");
} }
int smbus_wait_until_ready(u16 smbus_io_base) int smbus_wait_until_ready(u16 smbus_io_base)

8
southbridge/amd/sb600/stage1.c
View file

@ -69,7 +69,7 @@ static u8 get_sb600_revision(void)
{ {
u32 dev; u32 dev;
if (!pci_conf1_find_device(PCI_VENDOR_ID_ATI, 0x4385, &dev)){ if (!pci_conf1_find_device(PCI_VENDOR_ID_ATI, 0x4385, &dev)){
die("SMBUS controller not found\r\n"); die("SMBUS controller not found\n");
} }
return pci_conf1_read_config8(dev, 0x08); return pci_conf1_read_config8(dev, 0x08);
} }
@ -277,9 +277,9 @@ static void sb600_devices_por_init(void)
/* SMBus Device, BDF:0-20-0 */ /* SMBus Device, BDF:0-20-0 */
printk(BIOS_INFO, "sb600_devices_por_init(): SMBus Device, BDF:0-20-0\n"); printk(BIOS_INFO, "sb600_devices_por_init(): SMBus Device, BDF:0-20-0\n");
if (!pci_conf1_find_device(PCI_VENDOR_ID_ATI, 0x4385, &dev)){ if (!pci_conf1_find_device(PCI_VENDOR_ID_ATI, 0x4385, &dev)){
die("SMBUS controller not found\r\n"); die("SMBUS controller not found\n");
} }
printk(BIOS_INFO, "SMBus controller enabled, sb revision is 0x%x\r\n", printk(BIOS_INFO, "SMBus controller enabled, sb revision is 0x%x\n",
get_sb600_revision()); get_sb600_revision());
/* sbPorAtStartOfTblCfg */ /* sbPorAtStartOfTblCfg */
@ -402,7 +402,7 @@ static void sb600_devices_por_init(void)
pci_conf1_write_config8(dev, 0x7C, 0x05); pci_conf1_write_config8(dev, 0x7C, 0x05);
/* P2P Bridge, BDF:0-20-4, the configuration of the registers in this dev are copied from CIM, /* P2P Bridge, BDF:0-20-4, the configuration of the registers in this dev are copied from CIM,
* TODO: I don't know what are their mean? */ * TODO: I don't know what these mean? */
printk(BIOS_INFO, "sb600_devices_por_init(): P2P Bridge, BDF:0-20-4\n"); printk(BIOS_INFO, "sb600_devices_por_init(): P2P Bridge, BDF:0-20-4\n");
pci_conf1_find_device(PCI_VENDOR_ID_ATI, 0x4384, &dev); pci_conf1_find_device(PCI_VENDOR_ID_ATI, 0x4384, &dev);
/* I don't know why CIM tried to write into a read-only reg! */ /* I don't know why CIM tried to write into a read-only reg! */

2
southbridge/nvidia/mcp55/stage1.c
View file

@ -436,7 +436,7 @@ unsigned int get_sbdn(unsigned int bus)
*/ */
u32 bdf; u32 bdf;
if (!pci_conf1_find_device(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_MCP55_HT, &bdf)) { if (!pci_conf1_find_device(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_MCP55_HT, &bdf)) {
die("PCI_DEVICE_ID_NVIDIA_MCP55_HT not found\r\n"); die("PCI_DEVICE_ID_NVIDIA_MCP55_HT not found\n");
} }
return (bdf>>15) & 0x1f; return (bdf>>15) & 0x1f;

2
southbridge/nvidia/mcp55/stage1_smbus.c
View file

@ -192,7 +192,7 @@ void enable_smbus(void)
{ {
u32 bdf; u32 bdf;
if (!pci_conf1_find_device(0x10de, 0x0368, &bdf)) { if (!pci_conf1_find_device(0x10de, 0x0368, &bdf)) {
die("SMBUS controller not found\r\n"); die("SMBUS controller not found\n");
} }
printk(BIOS_DEBUG, "SMBus controller enabled\n"); printk(BIOS_DEBUG, "SMBus controller enabled\n");

6
superio/ite/it8716f/superio.c
View file

@ -74,13 +74,13 @@ static void init_ec(u16 base)
/* Read out current value of FAN_CTL control register (0x14). */ /* Read out current value of FAN_CTL control register (0x14). */
value = pnp_read_index(base, 0x14); value = pnp_read_index(base, 0x14);
printk(BIOS_DEBUG, "FAN_CTL: reg = 0x%04x, read value = 0x%02x\r\n", printk(BIOS_DEBUG, "FAN_CTL: reg = 0x%04x, read value = 0x%02x\n",
base + 0x14, value); base + 0x14, value);
/* Set FAN_CTL control register (0x14) polarity to high, and /* Set FAN_CTL control register (0x14) polarity to high, and
activate fans 1, 2 and 3. */ * activate fans 1, 2 and 3. */
pnp_write_index(base, 0x14, value | 0x87); pnp_write_index(base, 0x14, value | 0x87);
printk(BIOS_DEBUG, "FAN_CTL: reg = 0x%04x, writing value = 0x%02x\r\n", printk(BIOS_DEBUG, "FAN_CTL: reg = 0x%04x, writing value = 0x%02x\n",
base + 0x14, value | 0x87); base + 0x14, value | 0x87);
} }
#endif #endif

2
superio/winbond/w83627hf/superio.c
View file

@ -107,7 +107,7 @@ static void init_hwm(u16 base)
value &= 0xff & hwm_reg_values[i+1]; value &= 0xff & hwm_reg_values[i+1];
value |= 0xff & hwm_reg_values[i+2]; value |= 0xff & hwm_reg_values[i+2];
printk(BIOS_SPEW, "base = 0x%04x, reg = 0x%02x, value = 0x%02x\r\n", base, reg,value); printk(BIOS_SPEW, "base = 0x%04x, reg = 0x%02x, value = 0x%02x\n", base, reg,value);
pnp_write_index(base, reg, value); pnp_write_index(base, reg, value);
} }