From e5d40a545d1ae81e5fb44a68c073210ee4404be1 Mon Sep 17 00:00:00 2001
From: Patrick Rudolph <siro@das-labor.org>
Date: Tue, 14 Jun 2016 18:48:17 +0200
Subject: [PATCH] UPSTREAM: include/device/dram/ddr3: Add additional
 frequencies

IvyBridge memory controller supports more frequencies than SandyBridge.
Required for future patches.

Change-Id: I0bcb670c20407ec0aec20bae85c4cbe6ccc44b16
Original-Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Original-Reviewed-on: https://review.coreboot.org/15182
Original-Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
Original-Reviewed-by: Kysti Mlkki <kyosti.malkki@gmail.com>
(cherry-picked from commit 577aad6f132da51640b6fe5c72fa8f14718c5c34)
Signed-off-by: Martin Roth <martinroth@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/354196
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
---
 src/include/device/dram/ddr3.h | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/src/include/device/dram/ddr3.h b/src/include/device/dram/ddr3.h
index d58cdce8e1..eae7840fd2 100644
--- a/src/include/device/dram/ddr3.h
+++ b/src/include/device/dram/ddr3.h
@@ -35,9 +35,13 @@
  */
 #define TCK_1333MHZ     192
 #define TCK_1200MHZ     212
+#define TCK_1100MHZ     232
 #define TCK_1066MHZ     240
+#define TCK_1000MHZ     256
 #define TCK_933MHZ      274
+#define TCK_900MHZ      284
 #define TCK_800MHZ      320
+#define TCK_700MHZ      365
 #define TCK_666MHZ      384
 #define TCK_533MHZ      480
 #define TCK_400MHZ      640