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UPSTREAM: intel sandy/ivy: Increase XIP cache with USE_NATIVE_RAMINIT

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Compiled romstage is over 64kiB and exceeded XIP_ROM_SIZE,
so it was not entirely set WRPROT cacheable.

Reduces first boot raminit (including training) time by 400ms.

BUG=None
BRANCH=None
TEST=None

Signed-off-by: Kysti Mlkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/17488
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>

Change-Id: I5c4cbf581fc845150f207087c1527338ca364f60
Reviewed-on: https://chromium-review.googlesource.com/413253
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Kyösti Mälkki 2016-11-18 19:03:29 +02:00 • committed by chrome-bot
parent 2d1888247d
commit e49f26a35f
1 changed files with 4 additions and 0 deletions
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4
src/cpu/intel/model_206ax/Kconfig
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@ -25,6 +25,10 @@ config BOOTBLOCK_CPU_INIT
string
default "cpu/intel/model_206ax/bootblock.c"
config XIP_ROM_SIZE
hex
default 0x20000 if USE_NATIVE_RAMINIT
config SMM_TSEG_SIZE
hex
default 0x800000