diff --git a/mainboard/amd/Kconfig b/mainboard/amd/Kconfig index 10891ce4a4..81e9b70ef1 100644 --- a/mainboard/amd/Kconfig +++ b/mainboard/amd/Kconfig @@ -46,6 +46,17 @@ config BOARD_AMD_NORWICH help AMD Norwich Geode LX development board. +config BOARD_AMD_SERENGETI + bool "Serengeti" + select ARCH_X86 + select OPTION_TABLE + select CPU_AMD_K8 + select NORTHBRIDGE_AMD_K8 + select SOUTHBRIDGE_AMD_AMD8111 + select IOAPIC + help + AMD Serengeti + endchoice config MAINBOARD_DIR @@ -58,3 +69,8 @@ config MAINBOARD_DIR default amd/norwich depends BOARD_AMD_NORWICH +config MAINBOARD_DIR + string + default amd/serengeti + depends BOARD_AMD_SERENGETI + diff --git a/mainboard/amd/serengeti/Makefile b/mainboard/amd/serengeti/Makefile new file mode 100644 index 0000000000..fa49556691 --- /dev/null +++ b/mainboard/amd/serengeti/Makefile @@ -0,0 +1,41 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2006-2007 coresystems GmbH +## (Written by Stefan Reinauer for coresystems GmbH) +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +STAGE0_MAINBOARD_OBJ := $(obj)/mainboard/$(MAINBOARDDIR)/stage1.o \ + $(obj)/mainboard/$(MAINBOARDDIR)/option_table.o \ + $(obj)/southbridge/amd/amd8111/stage1_smbus.o \ + $(obj)/northbridge/amd/k8/coherent_ht.o \ + $(obj)/northbridge/amd/k8/incoherent_ht.o \ + $(obj)/lib/clog2.o + +INITRAM_SRC= $(src)/mainboard/$(MAINBOARDDIR)/initram.c \ + $(src)/northbridge/amd/k8/raminit.c \ + $(src)/arch/x86/pci_ops_conf1.c \ + $(src)/southbridge/amd/amd8111/stage1_smbus.c \ + $(src)/lib/clog2.c + + +STAGE2_MAINBOARD_SRC = + +$(obj)/coreboot.vpd: + $(Q)printf " BUILD DUMMY VPD\n" + $(Q)dd if=/dev/zero of=$(obj)/coreboot.vpd bs=256 count=1 $(SILENT) + diff --git a/mainboard/amd/serengeti/cmos.layout b/mainboard/amd/serengeti/cmos.layout new file mode 100644 index 0000000000..fe22993f2e --- /dev/null +++ b/mainboard/amd/serengeti/cmos.layout @@ -0,0 +1,119 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2007 AMD +## Written by Yinghai Lu for AMD. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +entries + +#start-bit length config config-ID name +#0 8 r 0 seconds +#8 8 r 0 alarm_seconds +#16 8 r 0 minutes +#24 8 r 0 alarm_minutes +#32 8 r 0 hours +#40 8 r 0 alarm_hours +#48 8 r 0 day_of_week +#56 8 r 0 day_of_month +#64 8 r 0 month +#72 8 r 0 year +#80 4 r 0 rate_select +#84 3 r 0 REF_Clock +#87 1 r 0 UIP +#88 1 r 0 auto_switch_DST +#89 1 r 0 24_hour_mode +#90 1 r 0 binary_values_enable +#91 1 r 0 square-wave_out_enable +#92 1 r 0 update_finished_enable +#93 1 r 0 alarm_interrupt_enable +#94 1 r 0 periodic_interrupt_enable +#95 1 r 0 disable_clock_updates +#96 288 r 0 temporary_filler +0 384 r 0 reserved_memory +384 1 e 4 boot_option +385 1 e 4 last_boot +386 1 e 1 ECC_memory +388 4 r 0 reboot_bits +392 3 e 5 baud_rate +395 1 e 1 hw_scrubber +396 1 e 1 interleave_chip_selects +397 2 e 8 max_mem_clock +399 1 e 2 dual_core +400 1 e 1 power_on_after_fail +412 4 e 6 debug_level +416 4 e 7 boot_first +420 4 e 7 boot_second +424 4 e 7 boot_third +428 4 h 0 boot_index +432 8 h 0 boot_countdown +440 4 e 9 slow_cpu +444 1 e 1 nmi +445 1 e 1 iommu +728 256 h 0 user_data +984 16 h 0 check_sum +# Reserve the extended AMD configuration registers +1000 24 r 0 reserved_memory + + + +enumerations + +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +5 0 115200 +5 1 57600 +5 2 38400 +5 3 19200 +5 4 9600 +5 5 4800 +5 6 2400 +5 7 1200 +6 6 Notice +6 7 Info +6 8 Debug +6 9 Spew +7 0 Network +7 1 HDD +7 2 Floppy +7 8 Fallback_Network +7 9 Fallback_HDD +7 10 Fallback_Floppy +#7 3 ROM +8 0 200Mhz +8 1 166Mhz +8 2 133Mhz +8 3 100Mhz +9 0 off +9 1 87.5% +9 2 75.0% +9 3 62.5% +9 4 50.0% +9 5 37.5% +9 6 25.0% +9 7 12.5% + +checksums + +checksum 392 1007 1008 + + diff --git a/mainboard/amd/serengeti/dts b/mainboard/amd/serengeti/dts new file mode 100644 index 0000000000..3409880cf0 --- /dev/null +++ b/mainboard/amd/serengeti/dts @@ -0,0 +1,56 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008 Ronald G. Minnich + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ +/*00:00.0 RAM memory: nVidia Corporation MCP55 Memory Controller (rev a1) +00:01.0 ISA bridge: nVidia Corporation MCP55 LPC Bridge (rev a2) +00:01.1 SMBus: nVidia Corporation MCP55 SMBus (rev a2) +00:02.0 USB Controller: nVidia Corporation MCP55 USB Controller (rev a1) +00:02.1 USB Controller: nVidia Corporation MCP55 USB Controller (rev a2) +00:04.0 IDE interface: nVidia Corporation MCP55 IDE (rev a1) +00:05.0 IDE interface: nVidia Corporation MCP55 SATA Controller (rev a2) +00:05.1 IDE interface: nVidia Corporation MCP55 SATA Controller (rev a2) +00:06.0 PCI bridge: nVidia Corporation MCP55 PCI bridge (rev a2) +00:06.1 Audio device: nVidia Corporation MCP55 High Definition Audio (rev a2) +00:08.0 Bridge: nVidia Corporation MCP55 Ethernet (rev a2) +00:0f.0 PCI bridge: nVidia Corporation MCP55 PCI Express bridge (rev a2) +00:18.0 Host bridge: Advanced Micro Devices [AMD] K8 [Athlon64/Opteron] HyperTransport Technology Configuration +00:18.1 Host bridge: Advanced Micro Devices [AMD] K8 [Athlon64/Opteron] Address Map +00:18.2 Host bridge: Advanced Micro Devices [AMD] K8 [Athlon64/Opteron] DRAM Controller +00:18.3 Host bridge: Advanced Micro Devices [AMD] K8 [Athlon64/Opteron] Miscellaneous Control +01:0a.0 FireWire (IEEE 1394): Texas Instruments TSB43AB23 IEEE-1394a-2000 Controller (PHY/Link) +02:00.0 VGA compatible controller: nVidia Corporation G72 [GeForce 7300 LE] (rev a1) +*/ + +/{ + mainboard_vendor = "AMD"; + mainboard_name = "Serengeti"; + cpus { }; + apic@0 { + }; + domain@0 { + pci@1,0{ + }; + pci@18,0 { + /config/("northbridge/amd/k8/pci"); + pci@0,0 { + /config/("southbridge/amd/amd8111/amd8111.dts"); + }; + }; + }; +}; diff --git a/mainboard/amd/serengeti/initram.c b/mainboard/amd/serengeti/initram.c new file mode 100644 index 0000000000..eeadb3b80e --- /dev/null +++ b/mainboard/amd/serengeti/initram.c @@ -0,0 +1,66 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007 Advanced Micro Devices, Inc. + * Copyright (C) 2007 Ronald G. Minnich + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#define _MAINOBJECT + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +# warning fix hard_reset +void hard_reset(void) +{ +} +void memreset_setup(void) +{ +} + +void memreset(int controllers, const struct mem_controller *ctrl) +{ +} + +void activate_spd_rom(const struct mem_controller *ctrl) +{ + /* nothing to do */ +} + + +/** + * main for initram for the Gigabyte m57sli. + */ +int main(void) +{ + printk(BIOS_DEBUG, "Hi there from stage1\n"); + post_code(POST_START_OF_MAIN); + + printk(BIOS_DEBUG, "stage1 returns\n"); + return 0; +} diff --git a/mainboard/amd/serengeti/stage1.c b/mainboard/amd/serengeti/stage1.c new file mode 100644 index 0000000000..9a85b5e2b2 --- /dev/null +++ b/mainboard/amd/serengeti/stage1.c @@ -0,0 +1,45 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007 Advanced Micro Devices, Inc. + * Copyright (C) 2008 Ronald G. Minnich + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + + +void hardware_stage1(void) +{ + post_code(POST_START_OF_MAIN); + +} + +void mainboard_pre_payload(void) +{ + banner(BIOS_DEBUG, "mainboard_pre_payload: done"); +} diff --git a/southbridge/amd/amd8111/amd8111.dts b/southbridge/amd/amd8111/amd8111.dts new file mode 100644 index 0000000000..62eb4c7a26 --- /dev/null +++ b/southbridge/amd/amd8111/amd8111.dts @@ -0,0 +1,23 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008 Ronald G. Minnich + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +{ + device_operations = "amd8111"; +}; diff --git a/southbridge/amd/amd8111/usb2.dts b/southbridge/amd/amd8111/usb2.dts index 165b0b5189..59670a490d 100644 --- a/southbridge/amd/amd8111/usb2.dts +++ b/southbridge/amd/amd8111/usb2.dts @@ -19,5 +19,5 @@ */ { - device_operations = "amd8111_usb"; + device_operations = "amd8111_usb2"; };