From dcedc08fe519841aeeed15db1889b1b6e6820d5f Mon Sep 17 00:00:00 2001 From: "Ronald G. Minnich" Date: Thu, 28 Jun 2007 01:59:46 +0000 Subject: [PATCH] This is an intermediate state for thie file. I am doing this commit since we have an ACK and since Marc Jones needs to work his magic. Signed-off-by: Ronald G. Minnich Acked-by: Uwe Hermann git-svn-id: svn://coreboot.org/repository/LinuxBIOSv3@391 f3766cd6-281f-0410-b1cd-43a5c92072e9 --- southbridge/amd/cs5536/cs5536.c | 16 +++++++++------- 1 file changed, 9 insertions(+), 7 deletions(-) diff --git a/southbridge/amd/cs5536/cs5536.c b/southbridge/amd/cs5536/cs5536.c index 740e980a25..8bf611801d 100644 --- a/southbridge/amd/cs5536/cs5536.c +++ b/southbridge/amd/cs5536/cs5536.c @@ -117,21 +117,21 @@ static void pm_chipset_init(void) /* PM_WKXD */ /* Make sure bits[3:0]=0000b to clear the */ /* saved Sx state */ - port = (PMS_IO_BASE + 0x034); + port = (PMS_IO_BASE + PM_WKXD); val = 0x0A0; /* 5ms */ outl(val, port); /* PM_WKD */ - port = (PMS_IO_BASE + 0x030); + port = (PMS_IO_BASE + PM_WKD); outl(val, port); /* PM_SED */ - port = (PMS_IO_BASE + 0x014); + port = (PMS_IO_BASE + PM_SED); val = 0x04601; /* 5ms, # of 3.57954MHz clock edges */ outl(val, port); /* PM_SIDD */ - port = (PMS_IO_BASE + 0x020); + port = (PMS_IO_BASE + PM_SIDD); val = 0x08C02; /* 10ms, # of 3.57954MHz clock edges */ outl(val, port); } @@ -519,7 +519,7 @@ void chipsetinit(void) post_code(P80_CHIPSET_INIT); dev = dev_find_device(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_CS5536_ISA, 0); if (! dev) { - printk(BIOS_ERR, "%s: Could not find the south bridge!\n", __FUNCTION)); + printk(BIOS_ERR, "%s: Could not find the south bridge!\n", __FUNCTION__); return; } sb = (struct southbridge_amd_cs5536_config *)dev->device_configuration; @@ -540,8 +540,10 @@ void chipsetinit(void) outl(GPIOL_2_SET, GPIO_IO_BASE + GPIOL_INPUT_ENABLE); outl(GPIOL_2_SET, GPIO_IO_BASE + GPIOL_IN_AUX1_SELECT); - /* Allow IO read and writes during a ATA DMA operation. */ - /* This could be done in the HD rom but do it here for easier debugging. */ + /* Allow IO read and writes during a ATA DMA operation. + * This could be done in the HD rom but + * do it here for easier debugging. + */ msrnum = ATA_SB_GLD_MSR_ERR; msr = rdmsr(msrnum); msr.lo &= ~0x100;