UPSTREAM: soc/intel/skylake: Expand USB OC pins definition to support PCH-H

Currently the USB OC pins definition only being defined up to OC3.
For PCH-H, OC4 and OC5 are needed, so add both into OC pin enum.

Changes is being verified and booted to Yocto with Saddle Brook.

BUG=none
BRANCH=none
TEST=none

Change-Id: I48ed19f800726d1220c0110cd3a7fdcb53b760dd
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: f296ce91b9
Original-Change-Id: Idaed6fa7dcddb9c688966e8bc59f656aec2b26eb
Original-Signed-off-by: Teo Boon Tiong <boon.tiong.teo@intel.com>
Original-Reviewed-on: https://review.coreboot.org/18364
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/445137

src/soc/intel/skylake/include/soc/usb.h

@@ -51,6 +51,8 @@ enum {
 	OC1,
 	OC2,
 	OC3,
+	OC4,
+	OC5,
 	OC_SKIP = 8, /* Skip OC programming */
 };