mirror of
https://github.com/fail0verflow/switch-coreboot.git
synced 2025-05-04 01:39:18 -04:00
Add (and use) the new PCI IDs:
- PCI_VENDOR_ID_CIRRUS - PCI_DEVICE_ID_CIRRUS_5446 Some minor cosmetic fixes (trivial). Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://coreboot.org/repository/LinuxBIOSv3@447 f3766cd6-281f-0410-b1cd-43a5c92072e9
This commit is contained in:
Uwe Hermann
parent
a167e27052
commit
d8196e2580
4 changed files with 143 additions and 141 deletions
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@ -11,151 +11,148 @@
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#ifndef DEVICE_PCI_IDS_H
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#define DEVICE_PCI_IDS_H
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/*
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* PCI Class, Vendor and Device IDs
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*
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* Please keep sorted.
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*/
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/* Device classes and subclasses. */
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#define PCI_CLASS_NOT_DEFINED 0x0000
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#define PCI_CLASS_NOT_DEFINED_VGA 0x0001
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#define PCI_CLASS_NOT_DEFINED 0x0000
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#define PCI_CLASS_NOT_DEFINED_VGA 0x0001
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#define PCI_BASE_CLASS_STORAGE 0x01
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#define PCI_CLASS_STORAGE_SCSI 0x0100
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#define PCI_CLASS_STORAGE_IDE 0x0101
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#define PCI_CLASS_STORAGE_FLOPPY 0x0102
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#define PCI_CLASS_STORAGE_IPI 0x0103
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#define PCI_CLASS_STORAGE_RAID 0x0104
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#define PCI_CLASS_STORAGE_SATA 0x0106
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#define PCI_CLASS_STORAGE_SATA_AHCI 0x010601
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#define PCI_CLASS_STORAGE_SAS 0x0107
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#define PCI_CLASS_STORAGE_OTHER 0x0180
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#define PCI_BASE_CLASS_STORAGE 0x01
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#define PCI_CLASS_STORAGE_SCSI 0x0100
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#define PCI_CLASS_STORAGE_IDE 0x0101
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#define PCI_CLASS_STORAGE_FLOPPY 0x0102
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#define PCI_CLASS_STORAGE_IPI 0x0103
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#define PCI_CLASS_STORAGE_RAID 0x0104
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#define PCI_CLASS_STORAGE_SATA 0x0106
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#define PCI_CLASS_STORAGE_SATA_AHCI 0x010601
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#define PCI_CLASS_STORAGE_SAS 0x0107
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#define PCI_CLASS_STORAGE_OTHER 0x0180
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#define PCI_BASE_CLASS_NETWORK 0x02
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#define PCI_CLASS_NETWORK_ETHERNET 0x0200
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#define PCI_CLASS_NETWORK_TOKEN_RING 0x0201
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#define PCI_CLASS_NETWORK_FDDI 0x0202
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#define PCI_CLASS_NETWORK_ATM 0x0203
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#define PCI_CLASS_NETWORK_OTHER 0x0280
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#define PCI_BASE_CLASS_NETWORK 0x02
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#define PCI_CLASS_NETWORK_ETHERNET 0x0200
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#define PCI_CLASS_NETWORK_TOKEN_RING 0x0201
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#define PCI_CLASS_NETWORK_FDDI 0x0202
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#define PCI_CLASS_NETWORK_ATM 0x0203
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#define PCI_CLASS_NETWORK_OTHER 0x0280
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#define PCI_BASE_CLASS_DISPLAY 0x03
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#define PCI_CLASS_DISPLAY_VGA 0x0300
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#define PCI_CLASS_DISPLAY_XGA 0x0301
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#define PCI_CLASS_DISPLAY_3D 0x0302
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#define PCI_CLASS_DISPLAY_OTHER 0x0380
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#define PCI_BASE_CLASS_DISPLAY 0x03
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#define PCI_CLASS_DISPLAY_VGA 0x0300
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#define PCI_CLASS_DISPLAY_XGA 0x0301
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#define PCI_CLASS_DISPLAY_3D 0x0302
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#define PCI_CLASS_DISPLAY_OTHER 0x0380
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#define PCI_BASE_CLASS_MULTIMEDIA 0x04
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#define PCI_CLASS_MULTIMEDIA_VIDEO 0x0400
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#define PCI_CLASS_MULTIMEDIA_AUDIO 0x0401
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#define PCI_CLASS_MULTIMEDIA_PHONE 0x0402
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#define PCI_CLASS_MULTIMEDIA_OTHER 0x0480
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#define PCI_BASE_CLASS_MULTIMEDIA 0x04
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#define PCI_CLASS_MULTIMEDIA_VIDEO 0x0400
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#define PCI_CLASS_MULTIMEDIA_AUDIO 0x0401
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#define PCI_CLASS_MULTIMEDIA_PHONE 0x0402
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#define PCI_CLASS_MULTIMEDIA_OTHER 0x0480
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#define PCI_BASE_CLASS_MEMORY 0x05
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#define PCI_CLASS_MEMORY_RAM 0x0500
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#define PCI_CLASS_MEMORY_FLASH 0x0501
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#define PCI_CLASS_MEMORY_OTHER 0x0580
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#define PCI_BASE_CLASS_MEMORY 0x05
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#define PCI_CLASS_MEMORY_RAM 0x0500
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#define PCI_CLASS_MEMORY_FLASH 0x0501
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#define PCI_CLASS_MEMORY_OTHER 0x0580
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#define PCI_BASE_CLASS_BRIDGE 0x06
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#define PCI_CLASS_BRIDGE_HOST 0x0600
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#define PCI_CLASS_BRIDGE_ISA 0x0601
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#define PCI_CLASS_BRIDGE_EISA 0x0602
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#define PCI_CLASS_BRIDGE_MC 0x0603
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#define PCI_CLASS_BRIDGE_PCI 0x0604
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#define PCI_CLASS_BRIDGE_PCMCIA 0x0605
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#define PCI_CLASS_BRIDGE_NUBUS 0x0606
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#define PCI_CLASS_BRIDGE_CARDBUS 0x0607
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#define PCI_CLASS_BRIDGE_RACEWAY 0x0608
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#define PCI_CLASS_BRIDGE_OTHER 0x0680
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#define PCI_BASE_CLASS_BRIDGE 0x06
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#define PCI_CLASS_BRIDGE_HOST 0x0600
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#define PCI_CLASS_BRIDGE_ISA 0x0601
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#define PCI_CLASS_BRIDGE_EISA 0x0602
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#define PCI_CLASS_BRIDGE_MC 0x0603
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#define PCI_CLASS_BRIDGE_PCI 0x0604
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#define PCI_CLASS_BRIDGE_PCMCIA 0x0605
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#define PCI_CLASS_BRIDGE_NUBUS 0x0606
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#define PCI_CLASS_BRIDGE_CARDBUS 0x0607
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#define PCI_CLASS_BRIDGE_RACEWAY 0x0608
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#define PCI_CLASS_BRIDGE_OTHER 0x0680
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#define PCI_BASE_CLASS_COMMUNICATION 0x07
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#define PCI_CLASS_COMMUNICATION_SERIAL 0x0700
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#define PCI_CLASS_COMMUNICATION_PARALLEL 0x0701
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#define PCI_CLASS_COMMUNICATION_MULTISERIAL 0x0702
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#define PCI_CLASS_COMMUNICATION_MODEM 0x0703
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#define PCI_CLASS_COMMUNICATION_OTHER 0x0780
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#define PCI_BASE_CLASS_COMMUNICATION 0x07
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#define PCI_CLASS_COMMUNICATION_SERIAL 0x0700
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#define PCI_CLASS_COMMUNICATION_PARALLEL 0x0701
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#define PCI_CLASS_COMMUNICATION_MULTISERIAL 0x0702
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#define PCI_CLASS_COMMUNICATION_MODEM 0x0703
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#define PCI_CLASS_COMMUNICATION_OTHER 0x0780
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#define PCI_BASE_CLASS_SYSTEM 0x08
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#define PCI_CLASS_SYSTEM_PIC 0x0800
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#define PCI_CLASS_SYSTEM_PIC_IOAPIC 0x080010
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#define PCI_CLASS_SYSTEM_PIC_IOXAPIC 0x080020
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#define PCI_CLASS_SYSTEM_DMA 0x0801
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#define PCI_CLASS_SYSTEM_TIMER 0x0802
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#define PCI_CLASS_SYSTEM_RTC 0x0803
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#define PCI_CLASS_SYSTEM_PCI_HOTPLUG 0x0804
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#define PCI_CLASS_SYSTEM_SDHCI 0x0805
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#define PCI_CLASS_SYSTEM_OTHER 0x0880
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#define PCI_BASE_CLASS_SYSTEM 0x08
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#define PCI_CLASS_SYSTEM_PIC 0x0800
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#define PCI_CLASS_SYSTEM_PIC_IOAPIC 0x080010
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#define PCI_CLASS_SYSTEM_PIC_IOXAPIC 0x080020
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#define PCI_CLASS_SYSTEM_DMA 0x0801
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#define PCI_CLASS_SYSTEM_TIMER 0x0802
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#define PCI_CLASS_SYSTEM_RTC 0x0803
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#define PCI_CLASS_SYSTEM_PCI_HOTPLUG 0x0804
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#define PCI_CLASS_SYSTEM_SDHCI 0x0805
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#define PCI_CLASS_SYSTEM_OTHER 0x0880
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#define PCI_BASE_CLASS_INPUT 0x09
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#define PCI_CLASS_INPUT_KEYBOARD 0x0900
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#define PCI_CLASS_INPUT_PEN 0x0901
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#define PCI_CLASS_INPUT_MOUSE 0x0902
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#define PCI_CLASS_INPUT_SCANNER 0x0903
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#define PCI_CLASS_INPUT_GAMEPORT 0x0904
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#define PCI_CLASS_INPUT_OTHER 0x0980
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#define PCI_BASE_CLASS_INPUT 0x09
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#define PCI_CLASS_INPUT_KEYBOARD 0x0900
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#define PCI_CLASS_INPUT_PEN 0x0901
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#define PCI_CLASS_INPUT_MOUSE 0x0902
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#define PCI_CLASS_INPUT_SCANNER 0x0903
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#define PCI_CLASS_INPUT_GAMEPORT 0x0904
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#define PCI_CLASS_INPUT_OTHER 0x0980
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#define PCI_BASE_CLASS_DOCKING 0x0a
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#define PCI_CLASS_DOCKING_GENERIC 0x0a00
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#define PCI_CLASS_DOCKING_OTHER 0x0a80
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#define PCI_BASE_CLASS_DOCKING 0x0a
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#define PCI_CLASS_DOCKING_GENERIC 0x0a00
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#define PCI_CLASS_DOCKING_OTHER 0x0a80
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#define PCI_BASE_CLASS_PROCESSOR 0x0b
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#define PCI_CLASS_PROCESSOR_386 0x0b00
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#define PCI_CLASS_PROCESSOR_486 0x0b01
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#define PCI_CLASS_PROCESSOR_PENTIUM 0x0b02
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#define PCI_CLASS_PROCESSOR_ALPHA 0x0b10
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#define PCI_CLASS_PROCESSOR_POWERPC 0x0b20
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#define PCI_CLASS_PROCESSOR_MIPS 0x0b30
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#define PCI_CLASS_PROCESSOR_CO 0x0b40
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#define PCI_BASE_CLASS_PROCESSOR 0x0b
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#define PCI_CLASS_PROCESSOR_386 0x0b00
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#define PCI_CLASS_PROCESSOR_486 0x0b01
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#define PCI_CLASS_PROCESSOR_PENTIUM 0x0b02
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#define PCI_CLASS_PROCESSOR_ALPHA 0x0b10
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#define PCI_CLASS_PROCESSOR_POWERPC 0x0b20
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#define PCI_CLASS_PROCESSOR_MIPS 0x0b30
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#define PCI_CLASS_PROCESSOR_CO 0x0b40
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#define PCI_BASE_CLASS_SERIAL 0x0c
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#define PCI_CLASS_SERIAL_FIREWIRE 0x0c00
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#define PCI_CLASS_SERIAL_FIREWIRE_OHCI 0x0c0010
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#define PCI_CLASS_SERIAL_ACCESS 0x0c01
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#define PCI_CLASS_SERIAL_SSA 0x0c02
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#define PCI_CLASS_SERIAL_USB 0x0c03
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#define PCI_CLASS_SERIAL_USB_UHCI 0x0c0300
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#define PCI_CLASS_SERIAL_USB_OHCI 0x0c0310
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#define PCI_CLASS_SERIAL_USB_EHCI 0x0c0320
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#define PCI_CLASS_SERIAL_FIBER 0x0c04
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#define PCI_CLASS_SERIAL_SMBUS 0x0c05
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#define PCI_BASE_CLASS_SERIAL 0x0c
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#define PCI_CLASS_SERIAL_FIREWIRE 0x0c00
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#define PCI_CLASS_SERIAL_FIREWIRE_OHCI 0x0c0010
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#define PCI_CLASS_SERIAL_ACCESS 0x0c01
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#define PCI_CLASS_SERIAL_SSA 0x0c02
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#define PCI_CLASS_SERIAL_USB 0x0c03
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#define PCI_CLASS_SERIAL_USB_UHCI 0x0c0300
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#define PCI_CLASS_SERIAL_USB_OHCI 0x0c0310
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#define PCI_CLASS_SERIAL_USB_EHCI 0x0c0320
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#define PCI_CLASS_SERIAL_FIBER 0x0c04
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#define PCI_CLASS_SERIAL_SMBUS 0x0c05
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#define PCI_BASE_CLASS_WIRELESS 0x0d
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#define PCI_CLASS_WIRELESS_RF_CONTROLLER 0x0d10
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#define PCI_CLASS_WIRELESS_WHCI 0x0d1010
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#define PCI_BASE_CLASS_INTELLIGENT 0x0e
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#define PCI_CLASS_INTELLIGENT_I2O 0x0e00
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#define PCI_BASE_CLASS_INTELLIGENT 0x0e
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#define PCI_CLASS_INTELLIGENT_I2O 0x0e00
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#define PCI_BASE_CLASS_SATELLITE 0x0f
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#define PCI_CLASS_SATELLITE_TV 0x0f00
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#define PCI_CLASS_SATELLITE_AUDIO 0x0f01
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#define PCI_CLASS_SATELLITE_VOICE 0x0f03
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#define PCI_CLASS_SATELLITE_DATA 0x0f04
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#define PCI_BASE_CLASS_SATELLITE 0x0f
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#define PCI_CLASS_SATELLITE_TV 0x0f00
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#define PCI_CLASS_SATELLITE_AUDIO 0x0f01
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#define PCI_CLASS_SATELLITE_VOICE 0x0f03
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#define PCI_CLASS_SATELLITE_DATA 0x0f04
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#define PCI_BASE_CLASS_CRYPT 0x10
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#define PCI_CLASS_CRYPT_NETWORK 0x1000
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#define PCI_CLASS_CRYPT_ENTERTAINMENT 0x1001
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#define PCI_CLASS_CRYPT_OTHER 0x1080
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#define PCI_BASE_CLASS_CRYPT 0x10
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#define PCI_CLASS_CRYPT_NETWORK 0x1000
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#define PCI_CLASS_CRYPT_ENTERTAINMENT 0x1001
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#define PCI_CLASS_CRYPT_OTHER 0x1080
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#define PCI_BASE_CLASS_SIGNAL_PROCESSING 0x11
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#define PCI_CLASS_SP_DPIO 0x1100
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#define PCI_CLASS_SP_OTHER 0x1180
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#define PCI_BASE_CLASS_SIGNAL_PROCESSING 0x11
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#define PCI_CLASS_SP_DPIO 0x1100
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#define PCI_CLASS_SP_OTHER 0x1180
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#define PCI_CLASS_OTHERS 0xff
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#define PCI_CLASS_OTHERS 0xff
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/* Vendors and devices. Sort key: vendor first, device next. */
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#define PCI_VENDOR_ID_AMD 0x1022
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#define PCI_DEVICE_ID_AMD_LXBRIDGE 0x2080
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#define PCI_DEVICE_ID_AMD_CS5536_ISA 0x2090
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#define PCI_DEVICE_ID_AMD_CS5536_FLASH 0x2091
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#define PCI_DEVICE_ID_AMD_CS5536_A0_IDE 0x2092
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#define PCI_DEVICE_ID_AMD_CS5536_AUDIO 0x2093
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#define PCI_DEVICE_ID_AMD_CS5536_OHCI 0x2094
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#define PCI_DEVICE_ID_AMD_CS5536_EHCI 0x2095
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#define PCI_DEVICE_ID_AMD_CS5536_UDC 0x2096
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#define PCI_DEVICE_ID_AMD_CS5536_OTG 0x2097
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#define PCI_DEVICE_ID_AMD_CS5536_B0_IDE 0x209A
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#define PCI_VENDOR_ID_AMD 0x1022
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#define PCI_DEVICE_ID_AMD_LXBRIDGE 0x2080
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#define PCI_DEVICE_ID_AMD_CS5536_ISA 0x2090
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#define PCI_DEVICE_ID_AMD_CS5536_FLASH 0x2091
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#define PCI_DEVICE_ID_AMD_CS5536_A0_IDE 0x2092
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#define PCI_DEVICE_ID_AMD_CS5536_AUDIO 0x2093
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#define PCI_DEVICE_ID_AMD_CS5536_OHCI 0x2094
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#define PCI_DEVICE_ID_AMD_CS5536_EHCI 0x2095
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#define PCI_DEVICE_ID_AMD_CS5536_UDC 0x2096
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#define PCI_DEVICE_ID_AMD_CS5536_OTG 0x2097
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#define PCI_DEVICE_ID_AMD_CS5536_B0_IDE 0x209A
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#define PCI_VENDOR_ID_CIRRUS 0x1013
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#define PCI_DEVICE_ID_CIRRUS_5446 0x00b8 /* Used by QEMU */
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#endif /* DEVICE_PCI_IDS_H */
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@ -19,11 +19,10 @@
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## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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##
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STAGE0_MAINBOARD_OBJ := $(obj)/mainboard/$(MAINBOARDDIR)/stage1.o
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STAGE0_MAINBOARD_OBJ :=\
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$(obj)/mainboard/$(MAINBOARDDIR)/stage1.o
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#
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# VPD or SIP ROM or ... how does NVIDIA call it?
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# VPD or SIP ROM or... how does NVIDIA call it?
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# Some space to cope with dirty southbridge tricks.
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# Do we want to put our own stuff there, too?
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#
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@ -38,12 +37,13 @@ $(obj)/linuxbios.vpd:
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# The initram file is always uncompressed. It belongs into the mainboard
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# directory and is built from what was auto.c in v2.
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#
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INITRAM_OBJ = $(obj)/mainboard/$(MAINBOARDDIR)/initram.o
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INITRAM_OBJ = $(obj)/mainboard/$(MAINBOARDDIR)/initram.o
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$(obj)/linuxbios.initram: $(obj)/stage0.init $(obj)/stage0.o $(INITRAM_OBJ)
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$(Q)# initram links against stage0
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$(Q)printf " LD $(subst $(shell pwd)/,,$(@))\n"
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$(Q)$(LD) -R $(obj)/stage0.o -Ttext 0x80000 $(INITRAM_OBJ) \
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$(Q)$(LD) -R $(obj)/stage0.o -Ttext 0x80000 $(INITRAM_OBJ) \
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--entry=main -o $(obj)/linuxbios.initram.o
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$(Q)printf " OBJCOPY $(subst $(shell pwd)/,,$(@))\n"
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$(Q)$(OBJCOPY) -O binary $(obj)/linuxbios.initram.o \
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@ -17,9 +17,11 @@
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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/* no printk allowed until hardware is ready; hardware is ready */
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/**
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* start up hardware needed for stage1
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* Start up hardware needed for stage1.
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*
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* No printk() allowed until hardware is ready; hardware is ready.
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* TODO: Fix above comment? It's unclear.
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*/
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void hardware_stage1(void)
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{
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#include <console.h>
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#include <device/device.h>
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#include <device/pci.h>
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#include <device/pci_ids.h>
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#include <string.h>
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#include <keyboard.h>
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@ -40,19 +41,21 @@ static void setup_onboard(struct device *dev)
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}
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static struct device_operations qemuvga_pci_ops_dev = {
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.constructor = default_device_constructor,
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.phase3_scan = 0,
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.phase4_read_resources = pci_dev_read_resources,
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.phase4_set_resources = pci_dev_set_resources,
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.phase4_enable_disable = setup_onboard,
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.phase5_enable_resources = pci_dev_enable_resources,
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.phase6_init = pci_dev_init,
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.ops_pci = &pci_dev_ops_pci,
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.constructor = default_device_constructor,
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.phase3_scan = 0,
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.phase4_read_resources = pci_dev_read_resources,
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.phase4_set_resources = pci_dev_set_resources,
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.phase4_enable_disable = setup_onboard,
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.phase5_enable_resources = pci_dev_enable_resources,
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.phase6_init = pci_dev_init,
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.ops_pci = &pci_dev_ops_pci,
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};
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struct constructor qemuvga_constructors[] = {
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{.id = {.type = DEVICE_ID_PCI,
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.u = {.pci = {.vendor = 0x1013,.device = 0x00b8}}},
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.u = {.pci = {.vendor = PCI_VENDOR_ID_CIRRUS,
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.device = PCI_DEVICE_ID_CIRRUS_5446}}},
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&qemuvga_pci_ops_dev},
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{.ops = 0},
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};
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Reference in a new issue