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amd/pi/hudson: Add hudson PM register defines
Clean up hudson PM register accesses with some register defines. Change-Id: I5ccf27a2463350baec53b7c79fe0fd4ec6c31306 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/19233 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
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2 changed files with 35 additions and 24 deletions
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@ -30,12 +30,6 @@
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#include "fchec.h"
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#include "fchec.h"
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#endif
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#endif
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/* Offsets from ACPI_MMIO_BASE
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* This is defined by AGESA, but we don't include AGESA headers to avoid
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* polluting the namespace.
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*/
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#define PM_MMIO_BASE 0xfed80300
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int acpi_get_sleep_type(void)
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int acpi_get_sleep_type(void)
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{
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{
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@ -76,19 +70,19 @@ void hudson_enable(device_t dev)
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/* turn off the SDHC controller in the PM reg */
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/* turn off the SDHC controller in the PM reg */
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u8 reg8;
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u8 reg8;
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if (sd_device_id == PCI_DEVICE_ID_AMD_HUDSON_SD) {
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if (sd_device_id == PCI_DEVICE_ID_AMD_HUDSON_SD) {
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reg8 = pm_read8(0xe7);
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reg8 = pm_read8(PM_HUD_SD_FLASH_CTRL);
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reg8 &= ~(1 << 0);
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reg8 &= ~BIT(0);
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pm_write8(0xe7, reg8);
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pm_write8(PM_HUD_SD_FLASH_CTRL, reg8);
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}
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}
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else if (sd_device_id == PCI_DEVICE_ID_AMD_YANGTZE_SD) {
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else if (sd_device_id == PCI_DEVICE_ID_AMD_YANGTZE_SD) {
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reg8 = pm_read8(0xe8);
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reg8 = pm_read8(PM_YANG_SD_FLASH_CTRL);
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reg8 &= ~(1 << 0);
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reg8 &= ~BIT(0);
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pm_write8(0xe8, reg8);
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pm_write8(PM_YANG_SD_FLASH_CTRL, reg8);
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}
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}
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/* remove device 0:14.7 from PCI space */
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/* remove device 0:14.7 from PCI space */
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reg8 = pm_read8(0xd3);
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reg8 = pm_read8(PM_MANUAL_RESET);
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reg8 &= ~(1 << 6);
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reg8 &= ~BIT(6);
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pm_write8(0xd3, reg8);
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pm_write8(PM_MANUAL_RESET, reg8);
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}
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}
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break;
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break;
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default:
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default:
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@ -102,24 +96,24 @@ static void hudson_init_acpi_ports(void)
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* ACPI tables are generated. Enable these ports indiscriminately.
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* ACPI tables are generated. Enable these ports indiscriminately.
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*/
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*/
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pm_write16(0x60, ACPI_PM_EVT_BLK);
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pm_write16(PM_EVT_BLK, ACPI_PM_EVT_BLK);
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pm_write16(0x62, ACPI_PM1_CNT_BLK);
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pm_write16(PM1_CNT_BLK, ACPI_PM1_CNT_BLK);
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pm_write16(0x64, ACPI_PM_TMR_BLK);
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pm_write16(PM_TMR_BLK, ACPI_PM_TMR_BLK);
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pm_write16(0x68, ACPI_GPE0_BLK);
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pm_write16(PM_GPE0_BLK, ACPI_GPE0_BLK);
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/* CpuControl is in \_PR.CP00, 6 bytes */
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/* CpuControl is in \_PR.CP00, 6 bytes */
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pm_write16(0x66, ACPI_CPU_CONTROL);
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pm_write16(PM_CPU_CTRL, ACPI_CPU_CONTROL);
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if (IS_ENABLED(CONFIG_HAVE_SMI_HANDLER)) {
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if (IS_ENABLED(CONFIG_HAVE_SMI_HANDLER)) {
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pm_write16(0x6a, ACPI_SMI_CTL_PORT);
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pm_write16(PM_ACPI_SMI_CMD, ACPI_SMI_CTL_PORT);
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hudson_enable_acpi_cmd_smi();
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hudson_enable_acpi_cmd_smi();
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} else {
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} else {
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pm_write16(0x6a, 0);
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pm_write16(PM_ACPI_SMI_CMD, 0);
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}
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}
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/* AcpiDecodeEnable, When set, SB uses the contents of the PM registers
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/* AcpiDecodeEnable, When set, SB uses the contents of the PM registers
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* at index 60-6B to decode ACPI I/O address. AcpiSmiEn & SmiCmdEn
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* at index 60-6B to decode ACPI I/O address. AcpiSmiEn & SmiCmdEn
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*/
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*/
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pm_write8(0x74, 1<<0 | 1<<1 | 1<<4 | 1<<2);
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pm_write8(PM_ACPI_CONF, BIT(0) | BIT(1) | BIT(4) | BIT(2));
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}
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}
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static void hudson_init(void *chip_info)
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static void hudson_init(void *chip_info)
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@ -22,6 +22,12 @@
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#include <device/device.h>
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#include <device/device.h>
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#include "chip.h"
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#include "chip.h"
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/* Offsets from ACPI_MMIO_BASE
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* This is defined by AGESA, but we don't include AGESA headers to avoid
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* polluting the namespace.
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*/
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#define PM_MMIO_BASE 0xfed80300
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/* Power management index/data registers */
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/* Power management index/data registers */
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#define BIOSRAM_INDEX 0xcd4
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#define BIOSRAM_INDEX 0xcd4
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#define BIOSRAM_DATA 0xcd5
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#define BIOSRAM_DATA 0xcd5
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@ -30,8 +36,19 @@
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#define PM2_INDEX 0xcd0
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#define PM2_INDEX 0xcd0
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#define PM2_DATA 0xcd1
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#define PM2_DATA 0xcd1
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#define HUDSON_ACPI_IO_BASE 0x800
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#define PM_SERIRQ_CONF 0x54
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#define PM_EVT_BLK 0x60
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#define PM1_CNT_BLK 0x62
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#define PM_TMR_BLK 0x64
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#define PM_CPU_CTRL 0x66
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#define PM_GPE0_BLK 0x68
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#define PM_ACPI_SMI_CMD 0x6A
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#define PM_ACPI_CONF 0x74
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#define PM_MANUAL_RESET 0xD3
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#define PM_HUD_SD_FLASH_CTRL 0xE7
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#define PM_YANG_SD_FLASH_CTRL 0xE8
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#define HUDSON_ACPI_IO_BASE 0x800
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#define ACPI_PM_EVT_BLK (HUDSON_ACPI_IO_BASE + 0x00) /* 4 bytes */
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#define ACPI_PM_EVT_BLK (HUDSON_ACPI_IO_BASE + 0x00) /* 4 bytes */
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#define ACPI_PM1_CNT_BLK (HUDSON_ACPI_IO_BASE + 0x04) /* 2 bytes */
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#define ACPI_PM1_CNT_BLK (HUDSON_ACPI_IO_BASE + 0x04) /* 2 bytes */
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#define ACPI_PM_TMR_BLK (HUDSON_ACPI_IO_BASE + 0x18) /* 4 bytes */
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#define ACPI_PM_TMR_BLK (HUDSON_ACPI_IO_BASE + 0x18) /* 4 bytes */
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