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Revert "UPSTREAM: soc/intel/apollolake: Add pmc_ipc device support"

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This reverts commit ed72d0db70.

This change causes the kernel to boot really slow. Maybe there is an
interrupt storm that prevents the kernel from making any
progress. Reverting until the proper kernel dependency is met.

BUG=chrome-os-partner:57364
BRANCH=None
TEST=Kernels boots to prompt fine on DVT.

Change-Id: I061c0b03b43b516a190b370c04888e73a410fcf1
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/391233
Reviewed-by: Duncan Laurie <dlaurie@google.com>
This commit is contained in:
Furquan Shaikh 2016-09-29 19:37:49 -07:00 • committed by chrome-bot
parent ca40148aa2
commit d7014ee1bb
2 changed files with 0 additions and 60 deletions
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57
src/soc/intel/apollolake/acpi/pmc_ipc.asl
View file

@ -1,57 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2016 Intel Corp.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; version 2 of
* the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <soc/iomap.h>
#define MAILBOX_DATA 0x7080
#define MAILBOX_INTF 0x7084
#define PMIO_LENGTH 0x80
Device (IPC1)
{
Name (_HID, "INT34D2")
Name (_CID, "INT34D2")
Name (_DDN, "Intel(R) IPC1 Controller")
Name (RBUF, ResourceTemplate ()
{
Memory32Fixed (ReadWrite, 0x0, 0x2000, IBAR)
Memory32Fixed (ReadWrite, 0x0, 0x4, MDAT)
Memory32Fixed (ReadWrite, 0x0, 0x4, MINF)
IO (Decode16, ACPI_PMIO_BASE, ACPI_PMIO_BASE + PMIO_LENGTH,
0x04, PMIO_LENGTH)
Memory32Fixed (ReadWrite, 0x0, 0x2000, SBAR)
Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive, , , )
{
PMC_INT
}
})
Method (_CRS, 0x0, NotSerialized)
{
CreateDwordField (^RBUF, ^IBAR._BAS, IBAS)
Store (PMC_BAR0, IBAS)
CreateDwordField (^RBUF, ^MDAT._BAS, MDBA)
Store (MCH_BASE_ADDR + MAILBOX_DATA, MDBA)
CreateDwordField (^RBUF, ^MINF._BAS, MIBA)
Store (MCH_BASE_ADDR + MAILBOX_INTF, MIBA)
CreateDwordField (^RBUF, ^SBAR._BAS, SBAS)
Store (PMC_SRAM_BASE_0, SBAS)
Return (^RBUF)
}
}

3
src/soc/intel/apollolake/acpi/southbridge.asl
View file

@ -40,9 +40,6 @@ Scope (\_SB)
#include "xhci.asl"
/* PMC IPC */
#include "pmc_ipc.asl"
/* LPC */
#include "lpc.asl"