mirror of
https://github.com/fail0verflow/switch-coreboot.git
synced 2025-05-04 01:39:18 -04:00
Fix up SMBUS. I had to yank the SHARED stuff -- it's not quite ready.
We will revisit it later. Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: svn://coreboot.org/repository/coreboot-v3@748 f3766cd6-281f-0410-b1cd-43a5c92072e9
This commit is contained in:
Ronald G. Minnich
parent
537773e6f1
commit
d5d2ba2cea
3 changed files with 175 additions and 154 deletions
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@ -22,6 +22,8 @@
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*/
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#include <device/smbus_def.h>
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#include <shared.h> /* We share symbols from stage 0 */
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#define SMBHSTSTAT 0x1
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#define SMBHSTPRTCL 0x0
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@ -41,157 +43,8 @@ static inline void smbus_delay(void)
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(void) inb(0x80);
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}
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static int smbus_wait_until_ready(u16 smbus_io_base)
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{
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unsigned long loops;
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loops = SMBUS_TIMEOUT;
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do {
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unsigned char val;
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smbus_delay();
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val = inb(smbus_io_base + SMBHSTSTAT);
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val &= 0x1f;
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if (val == 0) {
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return 0;
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}
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outb(val,smbus_io_base + SMBHSTSTAT);
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} while(--loops);
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return -2;
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}
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static int smbus_wait_until_done(u16 smbus_io_base)
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{
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unsigned long loops;
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loops = SMBUS_TIMEOUT;
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do {
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unsigned char val;
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smbus_delay();
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val = inb(smbus_io_base + SMBHSTSTAT);
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if ( (val & 0xff) != 0) {
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return 0;
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}
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} while(--loops);
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return -3;
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}
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static int do_smbus_recv_byte(u16 smbus_io_base, u8 device)
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{
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u8 global_status_register;
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u8 byte;
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/* set the device I'm talking too */
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outb(((device & 0x7f) << 1)|1 , smbus_io_base + SMBXMITADD);
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smbus_delay();
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/* byte data recv */
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outb(0x05, smbus_io_base + SMBHSTPRTCL);
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smbus_delay();
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/* poll for transaction completion */
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if (smbus_wait_until_done(smbus_io_base) < 0) {
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return -3;
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}
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global_status_register = inb(smbus_io_base + SMBHSTSTAT) & 0x80; /* lose check */
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/* read results of transaction */
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byte = inb(smbus_io_base + SMBHSTCMD);
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if (global_status_register != 0x80) { // loose check, otherwise it should be 0
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return -1;
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}
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return byte;
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}
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static int do_smbus_send_byte(u16 smbus_io_base, u8 device, u8 val)
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{
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u8 global_status_register;
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outb(val, smbus_io_base + SMBHSTDAT0);
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smbus_delay();
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/* set the command... */
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outb(val, smbus_io_base + SMBHSTCMD);
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smbus_delay();
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/* set the device I'm talking too */
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outb(((device & 0x7f) << 1) | 0, smbus_io_base + SMBXMITADD);
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smbus_delay();
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/* set up for a byte data write */
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outb(0x04, smbus_io_base + SMBHSTPRTCL);
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smbus_delay();
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/* poll for transaction completion */
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if (smbus_wait_until_done(smbus_io_base) < 0) {
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return -3;
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}
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global_status_register = inb(smbus_io_base + SMBHSTSTAT) & 0x80; /* lose check */;
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if (global_status_register != 0x80) {
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return -1;
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}
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return 0;
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}
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static int do_smbus_read_byte(u16 smbus_io_base, u8 device, u8 address)
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{
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u8 global_status_register;
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u8 byte;
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/* set the device I'm talking too */
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outb(((device & 0x7f) << 1)|1 , smbus_io_base + SMBXMITADD);
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smbus_delay();
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/* set the command/address... */
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outb(address & 0xff, smbus_io_base + SMBHSTCMD);
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smbus_delay();
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/* byte data read */
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outb(0x07, smbus_io_base + SMBHSTPRTCL);
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smbus_delay();
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/* poll for transaction completion */
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if (smbus_wait_until_done(smbus_io_base) < 0) {
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return -3;
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}
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global_status_register = inb(smbus_io_base + SMBHSTSTAT) & 0x80; /* lose check */
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/* read results of transaction */
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byte = inb(smbus_io_base + SMBHSTDAT0);
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if (global_status_register != 0x80) { // lose check, otherwise it should be 0
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return -1;
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}
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return byte;
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}
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static int do_smbus_write_byte(u16 smbus_io_base, u8 device, u8 address, u8 val)
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{
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u8 global_status_register;
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outb(val, smbus_io_base + SMBHSTDAT0);
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smbus_delay();
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/* set the device I'm talking too */
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outb(((device & 0x7f) << 1) | 0, smbus_io_base + SMBXMITADD);
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smbus_delay();
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outb(address & 0xff, smbus_io_base + SMBHSTCMD);
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smbus_delay();
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/* set up for a byte data write */
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outb(0x06, smbus_io_base + SMBHSTPRTCL);
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smbus_delay();
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/* poll for transaction completion */
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if (smbus_wait_until_done(smbus_io_base) < 0) {
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return -3;
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}
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global_status_register = inb(smbus_io_base + SMBHSTSTAT) & 0x80; /* lose check */;
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if (global_status_register != 0x80) {
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return -1;
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}
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return 0;
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}
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int do_smbus_recv_byte(u16 smbus_io_base, u8 device);
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int do_smbus_send_byte(u16 smbus_io_base, u8 device, u8 val);
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int do_smbus_read_byte(u16 smbus_io_base, u8 device, u8 address);
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int do_smbus_write_byte(u16 smbus_io_base, u8 device, u8 address, u8 val);
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void enable_smbus(void);
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150
southbridge/nvidia/mcp55/smbus.c
Normal file
150
southbridge/nvidia/mcp55/smbus.c
Normal file
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@ -0,0 +1,150 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2004 Tyan Computer
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* Written by Yinghai Lu <yhlu@tyan.com> for Tyan Computer.
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* Copyright (C) 2006,2007 AMD
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* Written by Yinghai Lu <yinghai.lu@amd.com> for AMD.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include <types.h>
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#include <lib.h>
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#include <console.h>
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#include <device/pci.h>
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#include <msr.h>
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#include <legacy.h>
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#include <device/pci_ids.h>
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#include <device/smbus.h>
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#include <io.h>
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#include <statictree.h>
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#include <config.h>
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#include "mcp55.h"
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#include "mcp55_smbus.h"
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static int lsmbus_recv_byte(struct device *dev)
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{
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unsigned device;
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struct resource *res;
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struct bus *pbus;
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device = dev->path.i2c.device;
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pbus = get_pbus_smbus(dev);
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res = find_resource(pbus->dev, 0x20 + (pbus->link * 4));
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return do_smbus_recv_byte(res->base, device);
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}
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static int lsmbus_send_byte(struct device *dev, u8 val)
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{
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unsigned device;
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struct resource *res;
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struct bus *pbus;
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device = dev->path.i2c.device;
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pbus = get_pbus_smbus(dev);
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res = find_resource(pbus->dev, 0x20 + (pbus->link * 4));
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return do_smbus_send_byte(res->base, device, val);
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}
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static int lsmbus_read_byte(struct device *dev, u8 address)
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{
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unsigned device;
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struct resource *res;
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struct bus *pbus;
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device = dev->path.i2c.device;
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pbus = get_pbus_smbus(dev);
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res = find_resource(pbus->dev, 0x20 + (pbus->link * 4));
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return do_smbus_read_byte(res->base, device, address);
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}
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static int lsmbus_write_byte(struct device *dev, u8 address, u8 val)
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{
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unsigned device;
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struct resource *res;
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struct bus *pbus;
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device = dev->path.i2c.device;
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pbus = get_pbus_smbus(dev);
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res = find_resource(pbus->dev, 0x20 + (pbus->link * 4));
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return do_smbus_write_byte(res->base, device, address, val);
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}
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static struct smbus_bus_operations lops_smbus_bus = {
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.recv_byte = lsmbus_recv_byte,
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.send_byte = lsmbus_send_byte,
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.read_byte = lsmbus_read_byte,
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.write_byte = lsmbus_write_byte,
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};
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#ifdef HAVE_ACPI_TABLES
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unsigned pm_base;
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#endif
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static void mcp55_sm_read_resources(struct device *dev)
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{
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struct resource *res;
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unsigned long index;
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/* Get the normal pci resources of this device */
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pci_dev_read_resources(dev);
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for (index = 0x60; index <= 0x68; index+=4) { // We got another 3.
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pci_get_resource(dev, index);
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}
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compact_resources(dev);
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}
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static void mcp55_sm_init(struct device *dev)
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{
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#ifdef CONFIG_HAVE_ACPI_TABLES
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struct resource *res;
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res = find_resource(dev, 0x60);
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if (res)
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pm_base = res->base;
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#endif
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#warning finish subsystem set in mcp55 smbus
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#if 0
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pci_write_config32(dev, 0x40,
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((device & 0xffff) << 16) | (vendor & 0xffff));
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#endif
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}
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struct device_operations mcp55_smbus = {
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.id = {.type = DEVICE_ID_PCI,
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{.pci = {.vendor = PCI_VENDOR_ID_NVIDIA,
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.device = PCI_DEVICE_ID_NVIDIA_MCP55_SM2}}},
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.constructor = default_device_constructor,
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.phase3_scan = scan_static_bus,
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.phase4_read_resources = mcp55_sm_read_resources,
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.phase4_set_resources = pci_dev_set_resources,
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.phase5_enable_resources = pci_dev_enable_resources,
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.phase6_init = mcp55_sm_init,
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.ops_pci = &pci_dev_ops_pci,
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.ops_smbus_bus = &lops_smbus_bus,
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};
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@ -247,3 +247,21 @@ u8 smbusx_write_byte(u8 smb_index, u8 device, u8 address, u8 val)
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return do_smbus_write_byte(SMBUS0_IO_BASE + (smb_index<<8), device, address, val);
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}
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/**
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* Read a byte from the SPD.
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*
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* For this chip, that is really just saying 'read a byte from SMBus'.
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* So we use smbus_read_byte(). Nota Bene: leave this here as a function
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* rather than a #define in an obscure location. This function is called
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* only a few dozen times, and it's not performance critical.
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*
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* @param device The device.
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* @param address The address.
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* @return The data from the SMBus packet area or an error of 0xff (i.e. -1).
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*/
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u8 spd_read_byte(u16 device, u8 address)
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{
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return smbus_read_byte(device, address);
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}
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