mirror of
https://github.com/fail0verflow/switch-coreboot.git
synced 2025-05-04 01:39:18 -04:00
These changes implement car in qemu. The implementation is in several
ways superior to v3, while lacking its completeness. But, one nice thing: no more included .S or .c files. It's all separate compilation. That should allow our Makefiles to work much better. Note that the current non-CAR implementation is the default and continues to work (tested FILO boot to Linux on both CAR and non-CAR). Index: src/mainboard/emulation/qemu-x86/Config.lb Change this to be sensitive to USE_DCACHE_RAM. All settings etc. that depend on this variable are grouped in one if, and the other parts (romcc etc.) are in the else. This change is a model of how we should be able to do other motherboards. Index: src/mainboard/emulation/qemu-x86/Options.lb add needed options. Index: src/mainboard/emulation/qemu-x86/failover.c remove code inclusion from this not-yet-used file. Index: src/mainboard/emulation/qemu-x86/rom.c This is the entry point for the rom-based code. Called stage1.c in v3. Index: src/lib/Config.lb change initobject to a .o from a .c; this fixed a build problem. Index: src/pc80/serial.c make uart_init non-static. Index: src/pc80/Config.lb add initobject Index: src/arch/i386/init/entry.S Entry point. Unify a bunch of files that were fiddly lttle includes. From v3. Index: src/arch/i386/init/ldscript.ld new file. The goal is to hang all init changes for CAR here, to minimize other changes to any other ldscript. Besides, putting this in init makes sense; entry and car are manage init. Index: src/arch/i386/init/car.S generic i386 car code from v3. Index: src/arch/i386/init/ldscript_fallback_cbfs.lb Fix what looks like a bug: this was not including the init.text section. Index: targets/emulation/qemu-x86/Config.lb push up the console loglevel. qemu is for debugging so we might as well get all the debugging we can. Index: targets/emulation/qemu-x86/Config-car.lb For CAR bullds. Signed-off-by: Ronald G. minnich <rminnich@gmail.com> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4357 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Ronald G. minnich
Ronald G. Minnich
parent
3ba18a67eb
commit
d41de2ea7a
13 changed files with 704 additions and 59 deletions
357
src/arch/i386/init/car.S
Normal file
357
src/arch/i386/init/car.S
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2000,2007 Ronald G. Minnich <rminnich@gmail.com>
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* Copyright (C) 2005 Eswar Nallusamy, LANL
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* Copyright (C) 2005 Tyan
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* (Written by Yinghai Lu <yhlu@tyan.com> for Tyan)
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* Copyright (C) 2007 coresystems GmbH
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* (Written by Stefan Reinauer <stepan@coresystems.de> for coresystems GmbH)
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* Copyright (C) 2008 Carl-Daniel Hailfinger
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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/* Init code - Switch CPU to protected mode and enable Cache-as-Ram (CAR). */
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#include <arch/intel.h>
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#define ROM_CODE_SEG 0x08
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#define ROM_DATA_SEG 0x10
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#define CACHE_RAM_CODE_SEG 0x18
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#define CACHE_RAM_DATA_SEG 0x20
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/* When we come here we are in protected mode. We expand the stack
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* and copy the data segment from ROM to the memory.
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*
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* After that, we call the chipset bootstrap routine that
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* does what is left of the chipset initialization.
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*
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* NOTE: Aligned to 4 so that we are sure that the prefetch
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* cache will be reloaded.
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*/
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.section .rom.text
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.align 4
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.globl protected_stage0
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protected_stage0:
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lgdt %cs:gdtptr
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ljmp $ROM_CODE_SEG, $__protected_stage0
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.globl __protected_stage0
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__protected_stage0:
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/* Save the BIST result. */
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movl %eax, %ebp
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intel_chip_post_macro(0x01)
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movw $ROM_DATA_SEG, %ax
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movw %ax, %ds
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movw %ax, %es
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movw %ax, %ss
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movw %ax, %fs
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movw %ax, %gs
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/* Restore the BIST value to %eax. */
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movl %ebp, %eax
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.align 4
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/* disable HyperThreading is done by eswar
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* the other is very similar to the AMD CAR, except remove amd specific msr
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*/
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#define CacheSize DCACHE_RAM_SIZE
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#define CacheBase DCACHE_RAM_BASE
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#include <cpu/x86/mtrr.h>
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/* Save the BIST result */
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movl %eax, %ebp
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CacheAsRam:
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/* Check whether the processor has HT capability */
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movl $01, %eax
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cpuid
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btl $28, %edx
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jnc NotHtProcessor
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bswapl %ebx
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cmpb $01, %bh
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jbe NotHtProcessor
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/* It is a HT processor; Send SIPI to the other logical processor
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* within this processor so that the CAR related common system
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* registers are programmed accordingly
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*/
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/* Use some register that is common to both logical processors
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* as semaphore. Refer Appendix B, Vol.3
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*/
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xorl %eax, %eax
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xorl %edx, %edx
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movl $0x250, %ecx
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wrmsr
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/* Figure out the logical AP's APIC ID; the following logic will work
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* only for processors with 2 threads.
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*
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* Refer to Vol 3. Table 7-1 for details about this logic
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*/
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movl $0xFEE00020, %esi
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movl (%esi), %ebx
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andl $0xFF000000, %ebx
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bswapl %ebx
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btl $0, %ebx
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jnc LogicalAP0
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andb $0xFE, %bl
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jmp SendSIPI
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LogicalAP0:
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orb $0x01, %bl
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SendSIPI:
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bswapl %ebx /* ebx - logical AP's APIC ID */
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/* Fill up the IPI command registers in the Local APIC mapped to
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* default address and issue SIPI to the other logical processor
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* within this processor die.
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*/
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RetrySIPI:
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movl %ebx, %eax
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movl $0xFEE00310, %esi
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movl %eax, (%esi)
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/* SIPI vector - F900:0000 */
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movl $0x000006F9, %eax
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movl $0xFEE00300, %esi
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movl %eax, (%esi)
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movl $0x30, %ecx
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SIPIDelay:
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pause
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decl %ecx
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jnz SIPIDelay
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movl (%esi), %eax
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andl $0x00001000, %eax
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jnz RetrySIPI
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/* Wait for the Logical AP to complete initialization */
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LogicalAPSIPINotdone:
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movl $0x250, %ecx
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rdmsr
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orl %eax, %eax
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jz LogicalAPSIPINotdone
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NotHtProcessor:
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/* Set the default memory type and enable fixed and variable MTRRs */
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movl $MTRRdefType_MSR, %ecx
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xorl %edx, %edx
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/* Enable Variable and Fixed MTRRs */
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movl $0x00000c00, %eax
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wrmsr
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/* Clear all MTRRs */
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xorl %edx, %edx
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movl $fixed_mtrr_msr, %esi
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clear_fixed_var_mtrr:
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lodsl (%esi), %eax
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testl %eax, %eax
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jz clear_fixed_var_mtrr_out
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movl %eax, %ecx
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xorl %eax, %eax
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wrmsr
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jmp clear_fixed_var_mtrr
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clear_fixed_var_mtrr_out:
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/* 0x06 is the WB IO type for a given 4k segment.
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* segs is the number of 4k segments in the area of the particular
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* register we want to use for CAR.
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* reg is the register where the IO type should be stored.
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*/
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.macro extractmask segs, reg
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.if \segs <= 0
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/* The xorl here is superfluous because at the point of first execution
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* of this macro, %eax and %edx are cleared. Later invocations of this
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* macro will have a monotonically increasing segs parameter.
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*/
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xorl \reg, \reg
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.elseif \segs == 1
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movl $0x06000000, \reg /* WB IO type */
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.elseif \segs == 2
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movl $0x06060000, \reg /* WB IO type */
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.elseif \segs == 3
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movl $0x06060600, \reg /* WB IO type */
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.elseif \segs >= 4
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movl $0x06060606, \reg /* WB IO type */
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.endif
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.endm
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/* size is the cache size in bytes we want to use for CAR.
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* windowoffset is the 32k-aligned window into CAR size
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*/
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.macro simplemask carsize, windowoffset
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/* DO NOT CHANGE THE FORMATTING of the two lines below! Whitespace is
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* interpreted as an argument delimiter by some versions of GNU as. */
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extractmask (((\carsize-\windowoffset)/0x1000)-4), %eax
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extractmask (((\carsize-\windowoffset)/0x1000)), %edx
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.endm
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#if CacheSize > 0x10000
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#error Invalid CAR size, must be at most 64k.
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#endif
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#if CacheSize < 0x1000
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#error Invalid CAR size, must be at least 4k. This is a processor limitation.
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#endif
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#if (CacheSize & (0x1000 - 1))
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#error Invalid CAR size, is not a multiple of 4k. This is a processor limitation.
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#endif
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#if CacheSize > 0x8000
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/* enable caching for 32K-64K using fixed mtrr */
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movl $0x268, %ecx /* fix4k_c0000*/
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simplemask CacheSize, 0x8000
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wrmsr
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#endif
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/* enable caching for 0-32K using fixed mtrr */
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movl $0x269, %ecx /* fix4k_c8000*/
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simplemask CacheSize, 0
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wrmsr
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#if defined(CONFIG_XIP_ROM_SIZE) && defined(CONFIG_XIP_ROM_BASE)
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/* enable write base caching so we can do execute in place
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* on the flash rom.
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*/
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movl $0x202, %ecx
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xorl %edx, %edx
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movl $(XIP_ROM_BASE | MTRR_TYPE_WRBACK), %eax
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wrmsr
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movl $0x203, %ecx
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movl $0x0000000f, %edx
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movl $(~(XIP_ROM_SIZE - 1) | 0x800), %eax
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wrmsr
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#endif /* XIP_ROM_SIZE && XIP_ROM_BASE */
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/* enable cache */
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movl %cr0, %eax
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andl $0x9fffffff,%eax
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movl %eax, %cr0
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/* Read the range with lodsl*/
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movl $CacheBase, %esi
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cld
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movl $(CacheSize>>2), %ecx
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rep lodsl
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/* Clear the range */
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movl $CacheBase, %edi
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movl $(CacheSize>>2), %ecx
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xorl %eax, %eax
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rep stosl
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/* TODO: make this a config variable */
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#if CONFIG_CARTEST
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/* check the cache as ram */
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movl $CacheBase, %esi
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movl $(CacheSize>>2), %ecx
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.xin1:
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movl %esi, %eax
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movl %eax, (%esi)
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decl %ecx
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je .xout1
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add $4, %esi
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jmp .xin1
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.xout1:
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movl $CacheBase, %esi
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// movl $(CacheSize>>2), %ecx
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movl $4, %ecx
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.xin1x:
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movl %esi, %eax
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movl $0x4000, %edx
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movb %ah, %al
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.testx1:
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outb %al, $0x80
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decl %edx
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jnz .testx1
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movl (%esi), %eax
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cmpb 0xff, %al
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je .xin2 /* dont show */
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movl $0x4000, %edx
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.testx2:
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outb %al, $0x80
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decl %edx
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jnz .testx2
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.xin2: decl %ecx
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je .xout1x
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add $4, %esi
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jmp .xin1x
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.xout1x:
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#endif
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movl $(CacheBase+CacheSize-4), %eax
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movl %eax, %esp
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/* Load a different set of data segments */
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movw $CACHE_RAM_DATA_SEG, %ax
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movw %ax, %ds
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movw %ax, %es
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movw %ax, %ss
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lout:
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/* Store zero for the pointer to the global variables. */
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pushl $0
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/* Restore the BIST result. */
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movl %ebp, %eax
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/* We need to set ebp? No need. */
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movl %esp, %ebp
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/* Third parameter: cpu #: 0 == BSP all other are APs.
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* 0 until SMP support is added.
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*/
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pushl $0
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/* Second parameter: init_detected */
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/* Store zero for the unused init_detected parameter. */
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pushl $0
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/* First parameter: bist */
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pushl %eax
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call main
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/* We will not go back. */
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fixed_mtrr_msr:
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.long 0x250, 0x258, 0x259
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.long 0x268, 0x269, 0x26A
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.long 0x26B, 0x26C, 0x26D
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.long 0x26E, 0x26F
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var_mtrr_msr:
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.long 0x200, 0x201, 0x202, 0x203
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.long 0x204, 0x205, 0x206, 0x207
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.long 0x208, 0x209, 0x20A, 0x20B
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.long 0x20C, 0x20D, 0x20E, 0x20F
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.long 0x000 /* NULL, end of table */
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156
src/arch/i386/init/entry.S
Normal file
156
src/arch/i386/init/entry.S
Normal file
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@ -0,0 +1,156 @@
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/*
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* This file is part of the coreboot project.
|
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*
|
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* Copyright (C) 1999 Ronald G. Minnich
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*
|
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* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
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*/
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#include <arch/rom_segs.h>
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.code16
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.globl _stage0
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_stage0:
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cli
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/* Save the BIST result. */
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movl %eax, %ebp;
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/* thanks to kmliu@sis.com.tw for this TLB fix */
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/* IMMEDIATELY invalidate the translation lookaside buffer (TLB) before
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* executing any further code. Even though paging is disabled we
|
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* could still get false address translations due to the TLB if we
|
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* didn't invalidate it.
|
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*/
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xorl %eax, %eax
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movl %eax, %cr3 /* Invalidate TLB. */
|
||||
|
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/* Switch to protected mode. */
|
||||
|
||||
/* NOTE: With GNU assembler version 2.15.94.0.2.2 (i386-redhat-linux)
|
||||
* using BFD version 2.15.94.0.2.2 20041220 this works fine without all
|
||||
* the ld hackery and other things. So leave it as is with this comment.
|
||||
*/
|
||||
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data32 lgdt %cs:gdtptr
|
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movl %cr0, %eax
|
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andl $0x7FFAFFD1, %eax /* PG, AM, WP, NE, TS, EM, MP = 0 */
|
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orl $0x60000001, %eax /* CD, NW, PE = 1 */
|
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movl %eax, %cr0
|
||||
|
||||
/* Restore BIST result. */
|
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movl %ebp, %eax
|
||||
|
||||
// port80_post(0x23)
|
||||
/* Now we are in protected mode. Jump to a 32 bit code segment. */
|
||||
data32 ljmp $ROM_CODE_SEG, $protected_stage0
|
||||
|
||||
/* I am leaving this weird jump in here in the event that future gas
|
||||
* bugs force it to be used.
|
||||
*/
|
||||
/* .byte 0x66 */
|
||||
.code32
|
||||
/* ljmp $ROM_CODE_SEG, $protected_stage0 */
|
||||
|
||||
/* .code16 */
|
||||
.align 4
|
||||
.globl gdt16
|
||||
gdt16 = . - _stage0
|
||||
gdt16x:
|
||||
.word gdt16xend - gdt16x -1 /* Compute the table limit. */
|
||||
.long gdt16x
|
||||
.word 0
|
||||
|
||||
/* selgdt 0x08, flat code segment */
|
||||
.word 0xffff, 0x0000
|
||||
.byte 0x00, 0x9b, 0xcf, 0x00
|
||||
|
||||
/* selgdt 0x10, flat data segment */
|
||||
.word 0xffff, 0x0000
|
||||
.byte 0x00, 0x93, 0xcf, 0x00
|
||||
gdt16xend:
|
||||
|
||||
/* From now on we are 32 bit. */
|
||||
.code32
|
||||
|
||||
/* We have two gdts where we could have one. That is ok.
|
||||
*
|
||||
* Let's not worry about this -- optimizing gdt is pointless since
|
||||
* we're only in it for a little bit.
|
||||
*
|
||||
* Btw. note the trick below: The GDT points to ITSELF, and the first
|
||||
* good descriptor is at offset 8. So you word-align the table, and
|
||||
* then because you chose 8, you get a nice 64-bit aligned GDT entry,
|
||||
* which is good as this is the size of the entry.
|
||||
* Just in case you ever wonder why people do this.
|
||||
*/
|
||||
.align 4
|
||||
.globl gdtptr
|
||||
.globl gdt_limit
|
||||
gdt_limit = gdt_end - gdt - 1 /* Compute the table limit. */
|
||||
|
||||
gdt:
|
||||
gdtptr:
|
||||
.word gdt_end - gdt -1 /* Compute the table limit. */
|
||||
.long gdt /* We know the offset. */
|
||||
.word 0
|
||||
|
||||
/* selgdt 0x08, flat code segment */
|
||||
.word 0xffff, 0x0000
|
||||
.byte 0x00, 0x9b, 0xcf, 0x00
|
||||
|
||||
/* selgdt 0x10, flat data segment */
|
||||
.word 0xffff, 0x0000
|
||||
.byte 0x00, 0x93, 0xcf, 0x00
|
||||
|
||||
/* selgdt 0x18, flat code segment for CAR */
|
||||
.word 0xffff, 0x0000
|
||||
.byte 0x00, 0x9b, 0xcf, 0x00
|
||||
|
||||
/* selgdt 0x20, flat data segment for CAR */
|
||||
.word 0xffff, 0x0000
|
||||
.byte 0x00, 0x93, 0xcf, 0x00
|
||||
gdt_end:
|
||||
|
||||
/* Reset vector. */
|
||||
|
||||
/*
|
||||
* RVECTOR: Size of reset vector, default is 0x10.
|
||||
* RESRVED: Size of vpd code, default is 0xf0.
|
||||
* BOOTBLK: Size of bootblock code, default is 0x1f00 (8k-256b).
|
||||
*/
|
||||
|
||||
SEGMENT_SIZE = 0x10000
|
||||
RVECTOR = 0x00010
|
||||
|
||||
/* Due to YET ANOTHER BUG in GNU bintools, you can NOT have a code16 here.
|
||||
* I think we should leave it this way forever, as the bugs come and
|
||||
* go -- and come again.
|
||||
*
|
||||
* .code16
|
||||
* .section ".rom.text"
|
||||
*/
|
||||
.section ".reset", "ax"
|
||||
.globl _resetjump
|
||||
_resetjump:
|
||||
/* GNU bintools bugs again. This jumps to stage0 - 2. Sigh. */
|
||||
/* jmp _stage0 */
|
||||
.byte 0xe9
|
||||
.int _stage0 - ( . + 2 )
|
||||
|
||||
/* Note: The above jump is hand coded to work around bugs in binutils.
|
||||
* 5 bytes are used for a 3 byte instruction. This works because x86
|
||||
* is little endian and allows us to use supported 32 bit relocations
|
||||
* instead of the weird 16 bit relocations that binutils does not
|
||||
* handle consistenly between versions because they are used so rarely.
|
||||
*/
|
||||
40
src/arch/i386/init/ldscript.ld
Normal file
40
src/arch/i386/init/ldscript.ld
Normal file
|
|
@ -0,0 +1,40 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2007 Ronald G. Minnich <rminnich@gmail.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
TARGET(binary)
|
||||
SECTIONS
|
||||
{
|
||||
/DISCARD/ : {
|
||||
*(.comment)
|
||||
*(.note.*)
|
||||
*(.note)
|
||||
}
|
||||
}
|
||||
|
||||
SECTIONS {
|
||||
_ROMTOP = 0xfffffff0;
|
||||
. = _ROMTOP;
|
||||
.resetvector . : {
|
||||
*(.reset)
|
||||
. = 15 ;
|
||||
BYTE(0x00);
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -46,6 +46,7 @@ SECTIONS
|
|||
*(.rom.text);
|
||||
*(.rom.data);
|
||||
*(.init.rodata.*);
|
||||
*(.init.text);
|
||||
*(.rodata.*);
|
||||
*(.rom.data.*);
|
||||
. = ALIGN(16);
|
||||
|
|
|
|||
|
|
@ -20,7 +20,7 @@ object version.o
|
|||
# Force version.o to recompile every time
|
||||
makedefine .PHONY : version.o
|
||||
|
||||
initobject uart8250.c
|
||||
initobject uart8250.o
|
||||
initobject memset.o
|
||||
initobject memcpy.o
|
||||
initobject memcmp.o
|
||||
|
|
|
|||
|
|
@ -1,3 +1,5 @@
|
|||
## we don't use USE_DCACHE_RAM by default
|
||||
default USE_DCACHE_RAM=0
|
||||
##
|
||||
## Compute the location and size of where this firmware image
|
||||
## (coreboot plus bootloader) will live in the boot rom chip.
|
||||
|
|
@ -42,61 +44,78 @@ driver mainboard.o
|
|||
if HAVE_PIRQ_TABLE object irq_tables.o end
|
||||
#object reset.o
|
||||
|
||||
|
||||
## ALL dependencies for USE_DCACHE_RAM go here.
|
||||
## That way, later, we can simply yank them if we wish.
|
||||
## We include the old-fashioned entry code in the ! USE_DCACHE_RAM case.
|
||||
## we do not use failover yet in this case. This is a work in progress.
|
||||
if USE_DCACHE_RAM
|
||||
##
|
||||
##
|
||||
mainboardinit arch/i386/init/entry.S
|
||||
mainboardinit arch/i386/init/car.S
|
||||
ldscript /arch/i386/init/ldscript.ld
|
||||
|
||||
## The main code for the rom section is called rom.c
|
||||
initobject rom.o
|
||||
else
|
||||
##
|
||||
## Romcc output
|
||||
##
|
||||
makerule ./failover.E
|
||||
depends "$(MAINBOARD)/failover.c ../romcc"
|
||||
action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
|
||||
end
|
||||
|
||||
makerule ./failover.inc
|
||||
depends "$(MAINBOARD)/failover.c ../romcc"
|
||||
action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
|
||||
end
|
||||
|
||||
makerule ./auto.E
|
||||
depends "$(MAINBOARD)/auto.c option_table.h ../romcc"
|
||||
action "../romcc -E -mcpu=i386 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
|
||||
end
|
||||
makerule ./auto.inc
|
||||
depends "$(MAINBOARD)/auto.c option_table.h ../romcc"
|
||||
action "../romcc -mcpu=i386 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
|
||||
end
|
||||
|
||||
##
|
||||
## Build our 16 bit and 32 bit coreboot entry code
|
||||
##
|
||||
mainboardinit cpu/x86/16bit/entry16.inc
|
||||
mainboardinit cpu/x86/32bit/entry32.inc
|
||||
ldscript /cpu/x86/16bit/entry16.lds
|
||||
ldscript /cpu/x86/32bit/entry32.lds
|
||||
|
||||
##
|
||||
## Build our reset vector (This is where coreboot is entered)
|
||||
##
|
||||
mainboardinit cpu/x86/16bit/reset16.inc
|
||||
ldscript /cpu/x86/16bit/reset16.lds
|
||||
|
||||
### Should this be in the northbridge code?
|
||||
mainboardinit arch/i386/lib/cpu_reset.inc
|
||||
|
||||
##
|
||||
## Setup RAM
|
||||
##
|
||||
mainboardinit cpu/x86/fpu/enable_fpu.inc
|
||||
mainboardinit ./auto.inc
|
||||
|
||||
## the id string will be in cbfs. We will expect flashrom to parse cbfs for the idstring in future.
|
||||
##
|
||||
## Include an id string (For safe flashing)
|
||||
##
|
||||
mainboardinit arch/i386/lib/id.inc
|
||||
ldscript /arch/i386/lib/id.lds
|
||||
|
||||
##
|
||||
## Romcc output
|
||||
## end of USE_DCACHE_RAM bits.
|
||||
##
|
||||
makerule ./failover.E
|
||||
depends "$(MAINBOARD)/failover.c ../romcc"
|
||||
action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
|
||||
end
|
||||
|
||||
makerule ./failover.inc
|
||||
depends "$(MAINBOARD)/failover.c ../romcc"
|
||||
action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
|
||||
end
|
||||
|
||||
makerule ./auto.E
|
||||
depends "$(MAINBOARD)/auto.c option_table.h ../romcc"
|
||||
action "../romcc -E -mcpu=i386 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
|
||||
end
|
||||
makerule ./auto.inc
|
||||
depends "$(MAINBOARD)/auto.c option_table.h ../romcc"
|
||||
action "../romcc -mcpu=i386 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
|
||||
end
|
||||
|
||||
##
|
||||
## Build our 16 bit and 32 bit coreboot entry code
|
||||
##
|
||||
mainboardinit cpu/x86/16bit/entry16.inc
|
||||
mainboardinit cpu/x86/32bit/entry32.inc
|
||||
ldscript /cpu/x86/16bit/entry16.lds
|
||||
ldscript /cpu/x86/32bit/entry32.lds
|
||||
|
||||
##
|
||||
## Build our reset vector (This is where coreboot is entered)
|
||||
##
|
||||
mainboardinit cpu/x86/16bit/reset16.inc
|
||||
ldscript /cpu/x86/16bit/reset16.lds
|
||||
|
||||
### Should this be in the northbridge code?
|
||||
mainboardinit arch/i386/lib/cpu_reset.inc
|
||||
|
||||
##
|
||||
## Include an id string (For safe flashing)
|
||||
##
|
||||
mainboardinit arch/i386/lib/id.inc
|
||||
ldscript /arch/i386/lib/id.lds
|
||||
|
||||
###
|
||||
### O.k. We aren't just an intermediary anymore!
|
||||
###
|
||||
|
||||
##
|
||||
## Setup RAM
|
||||
##
|
||||
mainboardinit cpu/x86/fpu/enable_fpu.inc
|
||||
mainboardinit ./auto.inc
|
||||
|
||||
##
|
||||
## Include the secondary Configuration files
|
||||
##
|
||||
|
|
|
|||
|
|
@ -41,7 +41,10 @@ uses CONFIG_PCI_OPTION_ROM_RUN_REALMODE
|
|||
|
||||
uses CONFIG_CONSOLE_SERIAL8250
|
||||
uses USE_DCACHE_RAM
|
||||
|
||||
uses DCACHE_RAM_BASE
|
||||
uses DCACHE_RAM_SIZE
|
||||
uses CONFIG_USE_INIT
|
||||
uses CONFIG_USE_PRINTK_IN_CAR
|
||||
|
||||
uses DEFAULT_CONSOLE_LOGLEVEL
|
||||
uses MAXIMUM_CONSOLE_LOGLEVEL
|
||||
|
|
@ -128,4 +131,12 @@ default CONFIG_ROM_PAYLOAD = 1
|
|||
default CC="$(CROSS_COMPILE)gcc -m32"
|
||||
default HOSTCC="gcc"
|
||||
|
||||
##
|
||||
## known-good settings for qemu
|
||||
default DCACHE_RAM_BASE=0x8f000
|
||||
default DCACHE_RAM_SIZE=0x1000
|
||||
|
||||
|
||||
|
||||
|
||||
end
|
||||
|
|
|
|||
|
|
@ -1,16 +1,14 @@
|
|||
#define ASSEMBLY 1
|
||||
#include <stdint.h>
|
||||
#include <device/pci_def.h>
|
||||
#include <device/pci_ids.h>
|
||||
#include <arch/io.h>
|
||||
#include "arch/romcc_io.h"
|
||||
#include "pc80/mc146818rtc_early.c"
|
||||
#include "cpu/x86/lapic/boot_cpu.c"
|
||||
/* no code inclusion allowed */
|
||||
//#include "pc80/mc146818rtc_early.c"
|
||||
//#include "cpu/x86/lapic/boot_cpu.c"
|
||||
|
||||
static void main(void)
|
||||
{
|
||||
/* for now, just always assume failure */
|
||||
|
||||
#if 0
|
||||
/* Is this a cpu reset? */
|
||||
if (cpu_init_detected()) {
|
||||
|
|
@ -27,3 +25,4 @@ static void main(void)
|
|||
}
|
||||
#endif
|
||||
}
|
||||
|
||||
|
|
|
|||
30
src/mainboard/emulation/qemu-x86/rom.c
Normal file
30
src/mainboard/emulation/qemu-x86/rom.c
Normal file
|
|
@ -0,0 +1,30 @@
|
|||
#include <stdint.h>
|
||||
#include <device/pci_def.h>
|
||||
#include <device/pci_ids.h>
|
||||
#include <arch/io.h>
|
||||
#include <device/pnp_def.h>
|
||||
#include <arch/hlt.h>
|
||||
#include <console/console.h>
|
||||
#include <cbfs.h>
|
||||
|
||||
/*
|
||||
*/
|
||||
void udelay(int usecs)
|
||||
{
|
||||
int i;
|
||||
for(i = 0; i < usecs; i++)
|
||||
outb(i&0xff, 0x80);
|
||||
}
|
||||
|
||||
void main(void)
|
||||
{
|
||||
int i;
|
||||
void uart_init(void);
|
||||
void (*start_address)();
|
||||
outb(5, 0x80);
|
||||
|
||||
uart_init();
|
||||
start_address = cbfs_load_stage("fallback/coreboot_ram");
|
||||
start_address();
|
||||
|
||||
}
|
||||
|
|
@ -17,3 +17,7 @@ end
|
|||
dir vga
|
||||
|
||||
object keyboard.o
|
||||
|
||||
if CONFIG_USE_INIT
|
||||
initobject serial.o
|
||||
end
|
||||
|
|
|
|||
|
|
@ -96,7 +96,7 @@ static void uart_init(void)
|
|||
/* CONFIG_USE_PRINTK_IN_CAR == 1 */
|
||||
|
||||
extern void uart8250_init(unsigned base_port, unsigned divisor, unsigned lcs);
|
||||
static void uart_init(void)
|
||||
void uart_init(void)
|
||||
{
|
||||
#if USE_OPTION_TABLE == 1
|
||||
static const unsigned char divisor[] = { 1,2,3,6,12,24,48,96 };
|
||||
|
|
|
|||
26
targets/emulation/qemu-x86/Config-car.lb
Normal file
26
targets/emulation/qemu-x86/Config-car.lb
Normal file
|
|
@ -0,0 +1,26 @@
|
|||
# This will make a target directory of ./emulation_qemu-x86
|
||||
|
||||
target qemu-x86-car
|
||||
mainboard emulation/qemu-x86
|
||||
|
||||
option USE_DCACHE_RAM=1
|
||||
option CONFIG_USE_INIT=1
|
||||
option ROM_SIZE=512*1024
|
||||
option CONFIG_USE_INIT=1
|
||||
option CONFIG_USE_PRINTK_IN_CAR=1
|
||||
|
||||
option CC="gcc -m32"
|
||||
|
||||
option HAVE_PIRQ_TABLE=1
|
||||
option IRQ_SLOT_COUNT=6
|
||||
|
||||
romimage "fallback"
|
||||
option USE_FALLBACK_IMAGE=1
|
||||
option ROM_IMAGE_SIZE=0x10000
|
||||
option COREBOOT_EXTRA_VERSION="-GRUB2"
|
||||
# payload /home/stepan/core.img
|
||||
payload ../payload.elf
|
||||
end
|
||||
|
||||
buildrom ./coreboot.rom ROM_SIZE "fallback"
|
||||
|
||||
|
|
@ -9,6 +9,8 @@ option CC="gcc -m32"
|
|||
|
||||
option HAVE_PIRQ_TABLE=1
|
||||
option IRQ_SLOT_COUNT=6
|
||||
option DEFAULT_CONSOLE_LOGLEVEL=9
|
||||
option MAXIMUM_CONSOLE_LOGLEVEL=9
|
||||
|
||||
romimage "normal"
|
||||
option COREBOOT_EXTRA_VERSION="-GRUB2"
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue