mirror of
https://github.com/fail0verflow/switch-coreboot.git
synced 2025-05-04 01:39:18 -04:00
Various cleanups and cosmetic fixes.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Corey Osgood <corey.osgood@gmail.com> git-svn-id: svn://coreboot.org/repository/LinuxBIOSv3@520 f3766cd6-281f-0410-b1cd-43a5c92072e9
This commit is contained in:
Uwe Hermann
parent
497cdb7484
commit
d26d82a4a6
12 changed files with 99 additions and 85 deletions
30
Kconfig
30
Kconfig
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@ -101,19 +101,23 @@ config PAYLOAD_PREPARSE_ELF
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depends EXPERT
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default n
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help
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Until now, LinuxBIOS has used elf for the payload. There are many problems
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this, not least being the inefficiency -- the ELF has to be decompressed to
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memory and then the segments have to be copied. Plus, lar can't see the segments
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in the elf -- to see all segments, you have to extract the elf and run readelf on it.
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There are problems with collisions of the decompressed ELF location in memory
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and the segment locations in memory.
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Finally, validation of the ELF is done at run time, once you have flashed the
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FLASH and rebooted the machine. Boot time is really not the time you want to find
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out your ELF payload is broken.
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With this option, LinuxBIOS will direct lar to break each elf segment into a LAR
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entry. ELF will not be used at all. Note that (for now) LinuxBIOS is backward
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compatible -- if you put an ELF payload in, LinuxBIOS can still parse it. We hope
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to remove ELF entirely in the future.
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Until now, LinuxBIOS has used ELF for the payload. There are many
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problems with this, not least being the inefficiency -- the ELF has
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to be decompressed to memory and then the segments have to be
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copied. Plus, lar can't see the segments in the ELF -- to see all
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segments, you have to extract the ELF and run readelf on it.
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There are problems with collisions of the decompressed ELF
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location in memory and the segment locations in memory.
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Finally, validation of the ELF is done at run time, once you have
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flashed the FLASH and rebooted the machine. Boot time is really
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not the time you want to find out your ELF payload is broken.
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With this option, LinuxBIOS will direct lar to break each ELF
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segment into a LAR entry. ELF will not be used at all. Note that
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(for now) LinuxBIOS is backward compatible -- if you put an ELF
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payload in, LinuxBIOS can still parse it. We hope to remove ELF
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entirely in the future.
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config PAYLOAD_ELF
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bool "An ELF executable payload file"
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2
README
2
README
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@ -102,7 +102,7 @@ Note: Currently only the x86 QEMU target is supported in LinuxBIOSv3.
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The 'flashrom' tool is located in util/flashrom where you can build it
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from source code by typing 'make'. Alternatively, your favorite Linux
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distribution might ship a 'flashrom' package which provides the 'flashrom'
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program in (e.g.) /usr/bin. On Debian GNU/Linux systems you can get
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program in (e.g.) /usr/sbin. On Debian GNU/Linux systems you can get
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the flashrom package via 'apt-get install flashrom'.
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@ -80,7 +80,7 @@ $(obj)/southbridge/%.o: $(src)/southbridge/%.c $(obj)/statictree.h
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#
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# RAM initialization code can not be linked at a specific address,
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# hence it has to be executed in place position independently.
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# hence it has to be executed in place (XIP) position independently.
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#
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$(obj)/%_xip.o: $(src)/%.c
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@ -19,6 +19,7 @@
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*/
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#define _MAINOBJECT
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#include <types.h>
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#include <lib.h>
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#include <console.h>
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@ -33,9 +34,11 @@
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#include <southbridge/amd/cs5536/cs5536.h>
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#include <northbridge/amd/geodelx/raminit.h>
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#define MANUALCONF 0 /* Do automatic strapped PLL config */
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#define PLLMSRHI 0x00001490 /* manual settings for the PLL */
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#define MANUALCONF 0 /* Do automatic strapped PLL config. */
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#define PLLMSRHI 0x00001490 /* Manual settings for the PLL */
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#define PLLMSRLO 0x02000030
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#define DIMM0 ((u8) 0xA0)
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#define DIMM1 ((u8) 0xA2)
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@ -52,10 +55,10 @@ int main(void)
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sdram_set_spd_registers(DIMM0, DIMM1);
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sdram_enable(DIMM0, DIMM1);
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/* Check low memory */
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//ram_check(0x00000000, 640*1024);
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/* Check low memory. */
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/* ram_check(0, 640 * 1024); */
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/* Switch from Cache as RAM to real RAM */
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/* Switch from Cache as RAM to real RAM. */
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printk(BIOS_SPEW, "Before wbinvd\n");
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__asm__("wbinvd\n");
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printk(BIOS_SPEW, "After wbinvd\n");
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@ -32,10 +32,10 @@
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#include <southbridge/amd/cs5536/cs5536.h>
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#include <superio/winbond/w83627hf/w83627hf.h>
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#define SERIAL_DEV W83627HF_SP1
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#define SERIAL_IOBASE 0x3f8
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#define SERIAL_DEV W83627HF_SP1
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#define SERIAL_IOBASE 0x3f8
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/* printk will not yet output anything */
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/* printk() will not yet output anything. */
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void hardware_stage1(void)
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{
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@ -46,9 +46,9 @@ void hardware_stage1(void)
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cs5536_stage1();
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/* NOTE: must do this AFTER the early_setup!
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* it is counting on some early MSR setup
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* for cs5536
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/*
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* NOTE: Must do this AFTER the early_setup! It is counting on some
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* early MSR setup for the CS5536.
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*/
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cs5536_disable_internal_uart();
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w83627hf_enable_serial(0x2e, SERIAL_DEV, SERIAL_IOBASE);
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@ -31,51 +31,46 @@
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#include <amd_geodelx.h>
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#include <northbridge/amd/geodelx/raminit.h>
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#define MANUALCONF 0 /* Do automatic strapped PLL config */
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#define PLLMSRHI 0x00001490 /* manual settings for the PLL */
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#define MANUALCONF 0 /* Do automatic strapped PLL config. */
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#define PLLMSRHI 0x00001490 /* Manual settings for the PLL */
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#define PLLMSRLO 0x02000030
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#define DIMM0 ((u8) 0xA0)
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#define DIMM1 ((u8) 0xA2)
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/**
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* Place holder in case we ever need it. Since this file is a
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* template for other motherboards, we want this here and we want the
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* call in the right place.
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*/
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* Placeholder in case we ever need it. Since this file is a template for
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* other boards, we want this here and we want the call in the right place.
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*/
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static void mb_gpio_init(void)
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{
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/* Early mainboard specific GPIO setup */
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}
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/**
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* main for initram for the amd norwich. It might seem that you
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* could somehow do these functions in, e.g., the cpu code, but the
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* order of operations and what those operations are is VERY strongly
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* mainboard dependent. It's best to leave it in the mainboard code.
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*/
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* Main for initram for the AMD Norwich. It might seem that you could somehow
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* do these functions in, e.g., the CPU code, but the order of operations and
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* what those operations are is VERY strongly mainboard dependent. It's best to
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* leave it in the mainboard code.
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*/
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int main(void)
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{
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u8 smb_devices[] = {
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DIMM0, DIMM1
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};
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u8 smb_devices[] = { DIMM0, DIMM1 };
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post_code(POST_START_OF_MAIN);
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system_preinit();
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mb_gpio_init();
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pll_reset(MANUALCONF, PLLMSRHI, PLLMSRLO);
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cpu_reg_init(0, DIMM0, DIMM1);
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sdram_set_registers();
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sdram_set_spd_registers(DIMM0, DIMM1);
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sdram_enable(DIMM0, DIMM1);
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/* Check low memory */
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/*ram_check(0x00000000, 640*1024); */
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/* Check low memory. */
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/* ram_check(0, 640 * 1024); */
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return 0;
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}
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@ -32,16 +32,17 @@
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void hardware_stage1(void)
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{
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post_code(POST_START_OF_MAIN);
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geodelx_msr_init();
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cs5536_stage1();
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/* NOTE: must do this AFTER the early_setup!
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* it is counting on some early MSR setup
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* for cs5536.
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*/
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/* We do this early for debug.
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* real setup should done in chipset init via config.lb
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/*
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* NOTE: Must do this AFTER the early_setup! It is counting on some
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* early MSR setup for the CS5536. We do this early for debug.
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* Real setup should be done in chipset init via Config.lb.
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*
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* TODO: Drop Config.lb reference, update comment.
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*/
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cs5536_setup_onchipuart();
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}
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@ -19,6 +19,7 @@
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*/
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#define _MAINOBJECT
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#include <types.h>
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#include <lib.h>
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#include <console.h>
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@ -31,19 +32,19 @@
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#include <southbridge/amd/cs5536/cs5536.h>
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#include <northbridge/amd/geodelx/raminit.h>
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#define MANUALCONF 0 /* Do automatic strapped PLL config */
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#define PLLMSRHI 0x00001490 /* manual settings for the PLL */
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#define MANUALCONF 0 /* Do automatic strapped PLL config. */
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#define PLLMSRHI 0x00001490 /* Manual settings for the PLL */
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#define PLLMSRLO 0x02000030
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#define DIVIL_LBAR_GPIO 0x5140000c
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#define DIMM0 ((u8) 0xA0)
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#define DIMM1 ((u8) 0xA2)
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/* this is an incredibly mainboard-specific number that has no appropriate place
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* outside this file.
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*/
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#define GPIO_BASE 0x6100
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#define GPIO_BASE 0x6100 /* Mainboard-specific */
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/* empty function to always fail smbus reads */
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/** Empty function to always fail SMBus reads. */
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int smbus_read_byte(unsigned device, unsigned address)
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{
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return -1;
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@ -52,14 +53,17 @@ int smbus_read_byte(unsigned device, unsigned address)
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static void init_gpio(void)
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{
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struct msr msr;
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printk(BIOS_DEBUG, "Initializing GPIO module...\n");
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// initialize the GPIO LBAR
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/* Initialize the GPIO LBAR. */
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msr.lo = GPIO_BASE;
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msr.hi = 0x0000f001;
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wrmsr(DIVIL_LBAR_GPIO, msr);
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msr = rdmsr(DIVIL_LBAR_GPIO);
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printk(BIOS_DEBUG, "DIVIL_LBAR_GPIO set to 0x%08x 0x%08x\n", msr.hi, msr.lo);
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printk(BIOS_DEBUG, "DIVIL_LBAR_GPIO set to 0x%08x 0x%08x\n",
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msr.hi, msr.lo);
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}
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static void sdram_hardwire(void)
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@ -67,16 +71,17 @@ static void sdram_hardwire(void)
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/* Total size of DIMM = 2^row address (byte 3) * 2^col address (byte 4) *
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* component Banks (byte 17) * module banks, side (byte 5) *
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* width in bits (byte 6,7)
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* = Density per side (byte 31) * number of sides (byte 5) */
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/* 1. Initialize GLMC registers base on SPD values, do one DIMM for now */
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struct msr msr;
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* = Density per side (byte 31) * number of sides (byte 5)
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*/
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/* Initialize GLMC registers based on SPD values, do one DIMM for now. */
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struct msr msr;
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msr.hi = 0x10075012;
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msr.lo = 0x00000040;
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wrmsr(MC_CF07_DATA, msr); /* GX3 */
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wrmsr(MC_CF07_DATA, msr); //GX3
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/* timing and mode ... */
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/* Timing and mode... */
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//msr = rdmsr(0x20000019);
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@ -109,11 +114,11 @@ static void sdram_hardwire(void)
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static const struct wmsr {
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u32 reg;
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struct msr msr;
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struct msr msr;
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} dbe61_msr[] = {
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{.reg = 0x10000020, {.lo = 0xfff80, .hi = 0x20000000}},
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{.reg = 0x10000020, {.lo = 0x00fff80, .hi = 0x20000000}},
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{.reg = 0x10000021, {.lo = 0x80fffe0, .hi = 0x20000000}},
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{.reg = 0x40000020, {.lo = 0xfff80, .hi = 0x20000000}},
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{.reg = 0x40000020, {.lo = 0x00fff80, .hi = 0x20000000}},
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{.reg = 0x40000021, {.lo = 0x80fffe0, .hi = 0x20000000}},
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};
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@ -129,14 +134,15 @@ int main(void)
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post_code(POST_START_OF_MAIN);
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system_preinit();
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pll_reset(MANUALCONF, PLLMSRHI, PLLMSRLO);
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cpu_reg_init(0, DIMM0, DIMM1);
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sdram_hardwire();
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/* Check low memory */
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/*ram_check(0x00000000, 640*1024); */
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/* ram_check(0, 640 * 1024); */
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init_gpio();
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return 0;
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}
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@ -34,9 +34,9 @@ static const struct wmsr {
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u32 reg;
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struct msr msr;
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} dbe61_msr[] = {
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{.reg = 0x10000020, {.lo = 0xfff80, .hi = 0x20000000}},
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{.reg = 0x10000020, {.lo = 0x00fff80, .hi = 0x20000000}},
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{.reg = 0x10000021, {.lo = 0x80fffe0, .hi = 0x20000000}},
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{.reg = 0x40000020, {.lo = 0xfff80, .hi = 0x20000000}},
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{.reg = 0x40000020, {.lo = 0x00fff80, .hi = 0x20000000}},
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{.reg = 0x40000021, {.lo = 0x80fffe0, .hi = 0x20000000}},
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};
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@ -55,9 +55,9 @@ void hardware_stage1(void)
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cs5536_stage1();
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/* NOTE: must do this AFTER the early_setup!
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* it is counting on some early MSR setup
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* for cs5536.
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/*
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* NOTE: Must do this AFTER the early_setup! It is counting on some
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* early MSR setup for the CS5536.
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*/
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cs5536_setup_onchipuart();
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}
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@ -18,6 +18,7 @@
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*/
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#define _MAINOBJECT
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#include <console.h>
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int main(void)
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@ -17,15 +17,16 @@
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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/* printk will not yet output anything */
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/* printk() will not yet output anything. */
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/**
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* start up hardware needed for stage1
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* Start up hardware needed for stage1.
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*/
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void hardware_stage1(void)
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{
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/* Nothing to do for Qemu */
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/* Nothing to do for QEMU. */
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}
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void disable_car(void)
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{
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}
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@ -32,11 +32,14 @@ static void setup_onboard(struct device *dev)
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struct pc_keyboard conf;
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printk(BIOS_INFO, "Init VGA device\n");
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dev->on_mainboard = 1;
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dev->rom_address = 0xc0000;
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// FIXME - this should be in superio some day
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// but since qemu has no superio.
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/*
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* FIXME: This should be in the Super I/O code some day,
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* but since QEMU has no Super I/O...
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*/
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init_pc_keyboard(0x60, 0x64, &conf);
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}
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