Various cleanups and cosmetic fixes.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Corey Osgood <corey.osgood@gmail.com>



git-svn-id: svn://coreboot.org/repository/LinuxBIOSv3@520 f3766cd6-281f-0410-b1cd-43a5c92072e9

Kconfig

@@ -101,19 +101,23 @@ config PAYLOAD_PREPARSE_ELF
 	depends EXPERT
 	default n
 	help
-	  Until now, LinuxBIOS has used elf for the payload. There are many problems 
+	  Until now, LinuxBIOS has used ELF for the payload. There are many
-	  this, not least being the inefficiency -- the ELF has to be decompressed to
+	  problems with this, not least being the inefficiency -- the ELF has
-	  memory and then the segments have to be copied. Plus, lar can't see the segments 
+	  to be decompressed to memory and then the segments have to be
-	  in the elf -- to see all segments, you have to extract the elf and run readelf on it.
+	  copied. Plus, lar can't see the segments in the ELF -- to see all
-	  There are problems with collisions of the decompressed ELF location in memory
+	  segments, you have to extract the ELF and run readelf on it.
-	  and the segment locations in memory. 
+
-	  Finally, validation of the ELF is done at run time, once you have flashed the 
+	  There are problems with collisions of the decompressed ELF
-	  FLASH and rebooted the machine. Boot time is really not the time you want to find 
+	  location in memory and the segment locations in memory.
-	  out your ELF payload is broken. 
+	  Finally, validation of the ELF is done at run time, once you have
-	  With this option, LinuxBIOS will direct lar to break each elf segment into a LAR 
+	  flashed the FLASH and rebooted the machine. Boot time is really
-	  entry. ELF will not be used at all. Note that (for now) LinuxBIOS is backward
+	  not the time you want to find out your ELF payload is broken.
-	  compatible -- if you put an ELF payload in, LinuxBIOS can still parse it. We hope
+
-	  to remove ELF entirely in the future. 
+	  With this option, LinuxBIOS will direct lar to break each ELF
+	  segment into a LAR entry. ELF will not be used at all. Note that
+	  (for now) LinuxBIOS is backward compatible -- if you put an ELF
+	  payload in, LinuxBIOS can still parse it. We hope to remove ELF
+	  entirely in the future.
 
 config PAYLOAD_ELF
 	bool "An ELF executable payload file"

README

@@ -102,7 +102,7 @@ Note: Currently only the x86 QEMU target is supported in LinuxBIOSv3.
   The 'flashrom' tool is located in util/flashrom where you can build it
   from source code by typing 'make'. Alternatively, your favorite Linux
   distribution might ship a 'flashrom' package which provides the 'flashrom'
-  program in (e.g.) /usr/bin. On Debian GNU/Linux systems you can get
+  program in (e.g.) /usr/sbin. On Debian GNU/Linux systems you can get
   the flashrom package via 'apt-get install flashrom'.
 
 

Rules.make

@@ -80,7 +80,7 @@ $(obj)/southbridge/%.o: $(src)/southbridge/%.c $(obj)/statictree.h
 
 #
 # RAM initialization code can not be linked at a specific address,
-# hence it has to be executed in place position independently.
+# hence it has to be executed in place (XIP) position independently.
 #
 
 $(obj)/%_xip.o: $(src)/%.c

mainboard/adl/msm800sev/initram.c

@@ -19,6 +19,7 @@
  */
 
 #define _MAINOBJECT
+
 #include <types.h>
 #include <lib.h>
 #include <console.h>
@@ -33,9 +34,11 @@
 #include <southbridge/amd/cs5536/cs5536.h>
 #include <northbridge/amd/geodelx/raminit.h>
 
-#define MANUALCONF 0		/* Do automatic strapped PLL config */
+#define MANUALCONF 0		/* Do automatic strapped PLL config. */
-#define PLLMSRHI 0x00001490	/* manual settings for the PLL */
+
+#define PLLMSRHI 0x00001490	/* Manual settings for the PLL */
 #define PLLMSRLO 0x02000030
+
 #define DIMM0 ((u8) 0xA0)
 #define DIMM1 ((u8) 0xA2)
 
@@ -52,10 +55,10 @@ int main(void)
 	sdram_set_spd_registers(DIMM0, DIMM1);
 	sdram_enable(DIMM0, DIMM1);
 
-	/* Check low memory */
+	/* Check low memory. */
-	//ram_check(0x00000000, 640*1024);
+	/* ram_check(0, 640 * 1024); */
 
-	/* Switch from Cache as RAM to real RAM */
+	/* Switch from Cache as RAM to real RAM. */
 	printk(BIOS_SPEW, "Before wbinvd\n");
 	__asm__("wbinvd\n");
 	printk(BIOS_SPEW, "After wbinvd\n");

mainboard/adl/msm800sev/stage1.c

@@ -32,10 +32,10 @@
 #include <southbridge/amd/cs5536/cs5536.h>
 #include <superio/winbond/w83627hf/w83627hf.h>
 
-#define SERIAL_DEV W83627HF_SP1
+#define SERIAL_DEV	W83627HF_SP1
-#define SERIAL_IOBASE 0x3f8
+#define SERIAL_IOBASE	0x3f8
 
-/* printk will not yet output anything */
+/* printk() will not yet output anything. */
 
 void hardware_stage1(void)
 {
@@ -46,9 +46,9 @@ void hardware_stage1(void)
 
 	cs5536_stage1();
 
-	/* NOTE: must do this AFTER the early_setup!
+	/*
-	 * it is counting on some early MSR setup
+	 * NOTE: Must do this AFTER the early_setup! It is counting on some
-	 * for cs5536
+	 * early MSR setup for the CS5536.
 	 */
 	cs5536_disable_internal_uart();
 	w83627hf_enable_serial(0x2e, SERIAL_DEV, SERIAL_IOBASE);

mainboard/amd/norwich/initram.c

@@ -31,51 +31,46 @@
 #include <amd_geodelx.h>
 #include <northbridge/amd/geodelx/raminit.h>
 
-#define MANUALCONF 0		/* Do automatic strapped PLL config */
+#define MANUALCONF 0		/* Do automatic strapped PLL config. */
-#define PLLMSRHI 0x00001490	/* manual settings for the PLL */
+
+#define PLLMSRHI 0x00001490	/* Manual settings for the PLL */
 #define PLLMSRLO 0x02000030
+
 #define DIMM0 ((u8) 0xA0)
 #define DIMM1 ((u8) 0xA2)
 
-
 /**
-  * Place holder in case we ever need it. Since this file is a
+ * Placeholder in case we ever need it. Since this file is a template for
-  * template for other motherboards, we want this here and we want the
+ * other boards, we want this here and we want the call in the right place.
-  * call in the right place.
+ */
-  */
-
 static void mb_gpio_init(void)
 {
 	/* Early mainboard specific GPIO setup */
 }
 
-/** 
+/**
-  * main for initram for the amd norwich.  It might seem that you
+ * Main for initram for the AMD Norwich. It might seem that you could somehow
-  * could somehow do these functions in, e.g., the cpu code, but the
+ * do these functions in, e.g., the CPU code, but the order of operations and
-  * order of operations and what those operations are is VERY strongly
+ * what those operations are is VERY strongly mainboard dependent. It's best to
-  * mainboard dependent. It's best to leave it in the mainboard code.
+ * leave it in the mainboard code.
-  */
+ */
 int main(void)
 {
-	u8 smb_devices[] =  {
+	u8 smb_devices[] = { DIMM0, DIMM1 };
-		DIMM0, DIMM1
-	};
 
 	post_code(POST_START_OF_MAIN);
 
 	system_preinit();
-
 	mb_gpio_init();
-
 	pll_reset(MANUALCONF, PLLMSRHI, PLLMSRLO);
-
 	cpu_reg_init(0, DIMM0, DIMM1);
 
 	sdram_set_registers();
 	sdram_set_spd_registers(DIMM0, DIMM1);
 	sdram_enable(DIMM0, DIMM1);
-	/* Check low memory */
+
-	/*ram_check(0x00000000, 640*1024); */
+	/* Check low memory. */
+	/* ram_check(0, 640 * 1024); */
 
 	return 0;
 }

mainboard/amd/norwich/stage1.c

@@ -32,16 +32,17 @@
 void hardware_stage1(void)
 {
 	post_code(POST_START_OF_MAIN);
+
 	geodelx_msr_init();
 
 	cs5536_stage1();
 
-	/* NOTE: must do this AFTER the early_setup!
+	/*
-	 * it is counting on some early MSR setup
+	 * NOTE: Must do this AFTER the early_setup! It is counting on some
-	 * for cs5536.
+	 * early MSR setup for the CS5536. We do this early for debug. 
-	 */
+	 * Real setup should be done in chipset init via Config.lb.
-	/* We do this early for debug. 
+	 *
-	 * real setup should done in chipset init via config.lb 
+	 * TODO: Drop Config.lb reference, update comment.
 	 */
 	cs5536_setup_onchipuart();
 }

mainboard/artecgroup/dbe61/initram.c

@@ -19,6 +19,7 @@
  */
 
 #define _MAINOBJECT
+
 #include <types.h>
 #include <lib.h>
 #include <console.h>
@@ -31,19 +32,19 @@
 #include <southbridge/amd/cs5536/cs5536.h>
 #include <northbridge/amd/geodelx/raminit.h>
 
-#define MANUALCONF 0		/* Do automatic strapped PLL config */
+#define MANUALCONF 0		/* Do automatic strapped PLL config. */
-#define PLLMSRHI 0x00001490	/* manual settings for the PLL */
+
+#define PLLMSRHI 0x00001490	/* Manual settings for the PLL */
 #define PLLMSRLO 0x02000030
+
 #define DIVIL_LBAR_GPIO		0x5140000c
+
 #define DIMM0 ((u8) 0xA0)
 #define DIMM1 ((u8) 0xA2)
 
-/* this is an incredibly mainboard-specific number that has no appropriate place
+#define GPIO_BASE		0x6100 /* Mainboard-specific */
-  * outside this file. 
-  */
-#define GPIO_BASE            0x6100
 
-/* empty function to always fail smbus reads */
+/** Empty function to always fail SMBus reads. */
 int smbus_read_byte(unsigned device, unsigned address)
 {
 	return -1;
@@ -52,14 +53,17 @@ int smbus_read_byte(unsigned device, unsigned address)
 static void init_gpio(void)
 {
 	struct msr msr;
+
 	printk(BIOS_DEBUG, "Initializing GPIO module...\n");
 
-	// initialize the GPIO LBAR
+	/* Initialize the GPIO LBAR. */
 	msr.lo = GPIO_BASE;
 	msr.hi = 0x0000f001;
 	wrmsr(DIVIL_LBAR_GPIO, msr);
 	msr = rdmsr(DIVIL_LBAR_GPIO);
-	printk(BIOS_DEBUG, "DIVIL_LBAR_GPIO set to 0x%08x 0x%08x\n", msr.hi, msr.lo);
+
+	printk(BIOS_DEBUG, "DIVIL_LBAR_GPIO set to 0x%08x 0x%08x\n",
+	       msr.hi, msr.lo);
 }
 
 static void sdram_hardwire(void)
@@ -67,16 +71,17 @@ static void sdram_hardwire(void)
 	/* Total size of DIMM = 2^row address (byte 3) * 2^col address (byte 4) *
 	 *                      component Banks (byte 17) * module banks, side (byte 5) *
 	 *                      width in bits (byte 6,7)
-	 *                    = Density per side (byte 31) * number of sides (byte 5) */
+	 *                    = Density per side (byte 31) * number of sides (byte 5)
-	/* 1. Initialize GLMC registers base on SPD values, do one DIMM for now */
+	 */
-	struct msr  msr;
+
+	/* Initialize GLMC registers based on SPD values, do one DIMM for now. */
+	struct msr msr;
 
 	msr.hi = 0x10075012;
 	msr.lo = 0x00000040;
-	
+	wrmsr(MC_CF07_DATA, msr);	/* GX3 */
-	wrmsr(MC_CF07_DATA, msr);		//GX3
 
-	/* timing and mode ... */
+	/* Timing and mode... */
 
 	//msr = rdmsr(0x20000019);
 	
@@ -109,11 +114,11 @@ static void sdram_hardwire(void)
 
 static const struct wmsr {
 	u32 reg;
-	struct msr  msr;
+	struct msr msr;
 } dbe61_msr[] = {
-	{.reg = 0x10000020, {.lo = 0xfff80, .hi = 0x20000000}},
+	{.reg = 0x10000020, {.lo = 0x00fff80, .hi = 0x20000000}},
 	{.reg = 0x10000021, {.lo = 0x80fffe0, .hi = 0x20000000}},
-	{.reg = 0x40000020, {.lo = 0xfff80, .hi = 0x20000000}},
+	{.reg = 0x40000020, {.lo = 0x00fff80, .hi = 0x20000000}},
 	{.reg = 0x40000021, {.lo = 0x80fffe0, .hi = 0x20000000}},
 };
 
@@ -129,14 +134,15 @@ int main(void)
 	post_code(POST_START_OF_MAIN);
 
 	system_preinit();
-
 	pll_reset(MANUALCONF, PLLMSRHI, PLLMSRLO);
-
 	cpu_reg_init(0, DIMM0, DIMM1);
 
 	sdram_hardwire();
+
 	/* Check low memory */
-	/*ram_check(0x00000000, 640*1024); */
+	/* ram_check(0, 640 * 1024); */
+
 	init_gpio();
+
 	return 0;
 }

mainboard/artecgroup/dbe61/stage1.c

@@ -34,9 +34,9 @@ static const struct wmsr {
 	u32 reg;
 	struct msr  msr;
 } dbe61_msr[] = {
-	{.reg = 0x10000020, {.lo = 0xfff80, .hi = 0x20000000}},
+	{.reg = 0x10000020, {.lo = 0x00fff80, .hi = 0x20000000}},
 	{.reg = 0x10000021, {.lo = 0x80fffe0, .hi = 0x20000000}},
-	{.reg = 0x40000020, {.lo = 0xfff80, .hi = 0x20000000}},
+	{.reg = 0x40000020, {.lo = 0x00fff80, .hi = 0x20000000}},
 	{.reg = 0x40000021, {.lo = 0x80fffe0, .hi = 0x20000000}},
 };
 
@@ -55,9 +55,9 @@ void hardware_stage1(void)
 
 	cs5536_stage1();
 
-	/* NOTE: must do this AFTER the early_setup!
+	/*
-	 * it is counting on some early MSR setup
+	 * NOTE: Must do this AFTER the early_setup! It is counting on some
-	 * for cs5536.
+	 * early MSR setup for the CS5536.
 	 */
 	cs5536_setup_onchipuart();
 }

mainboard/emulation/qemu-x86/initram.c

@@ -18,6 +18,7 @@
  */
 
 #define _MAINOBJECT
+
 #include <console.h>
 
 int main(void)

mainboard/emulation/qemu-x86/stage1.c

@@ -17,15 +17,16 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
 
-/* printk will not yet output anything */
+/* printk() will not yet output anything. */
 
 /** 
- * start up hardware needed for stage1
+ * Start up hardware needed for stage1.
  */
 void hardware_stage1(void)
 {
-	/* Nothing to do for Qemu */
+	/* Nothing to do for QEMU. */
 }
+
 void disable_car(void)
 {
 }

mainboard/emulation/qemu-x86/vga.c

@@ -32,11 +32,14 @@ static void setup_onboard(struct device *dev)
 	struct pc_keyboard conf;
 
 	printk(BIOS_INFO, "Init VGA device\n");
+
 	dev->on_mainboard = 1;
 	dev->rom_address = 0xc0000;
 
-	// FIXME - this should be in superio some day
+	/*
-	// but since qemu has no superio.
+	 * FIXME: This should be in the Super I/O code some day,
+	 * but since QEMU has no Super I/O...
+	 */
 	init_pc_keyboard(0x60, 0x64, &conf);
 }